On Fri, Jul 8, 2011 at 4:10 PM, Mahr, Stefan <stefan.m...@sphairon.com> wrote:
>>> - buf_set_u32 and buf_get_u32 make sure that data is in host endianness
>> Why ? Don't we want the data to be in target endianess ?
>
>>> You need swapping when reading and comparing debug registers or send code
>>> to MIPS CPU.
>> Can you give the example of some of these comparisons in the source
>> code ? You are referring to some comparisons in mips32_pracc.c ?
>
> example:
>
> mips_m4k.c: mips_m4k_poll
>
> mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
> retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
> ...
> if (ejtag_ctrl & EJTAG_CTRL_ROCC)
> {...
>
> ejtag_ctrl is host endian uint32. If mips_ejtag_drscan_32 would be in
> target endianness you need to swap here or write and use a new function
> that does swapping.
I agreee. Code like this is present on even lower level, im mips32_pracc.c, like
while (1)
{
retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (retval != ERROR_OK)
return retval;
if (ejtag_ctrl & EJTAG_CTRL_PRACC)
break;
if ( (timeout = timeval_ms()-then) > 1000 )
{
LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
return ERROR_JTAG_DEVICE_ERROR;
}
}
It has to be that way - so code must be in the host endianess right
after drscan.
Is this swap to host endianess done by buf_get_u32() in
mips_ejtag_drscan_32() after the queue has been executed ?
BR,
Drasko
_______________________________________________
Openocd-development mailing list
Openocd-development@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/openocd-development
