Hi all,
I am happy to present you several exciting enhancements to the MIPS32 target.
Most notably :
1) Implemented mips32_cp0_read() and mips32_cp0_write() routines that
can affect CP0 copro regs.
2) Implemented command interfaces for these commands, so that they can
be called from Telnet interface
3) Implemented cache synchronization, so that we can now support soft
breaks on cached regions. Linux can be debugged fine now.
All this has been discussed before on ML.
I have split all in logically independent commits, so that it can be
more easy integrated into the master (I tested each commit
independently, and overall version).
In the end, I rebased to souceforge's master, so all you have to do is
to pull the changes from my github branch.
BR,
Drasko
The following changes since commit ac43d7a69fca52df1ad287b51c44013653ad2f61:
Drasko DRASKOVIC (1):
mips_m4k and arm7_9 : Fix soft bkpt endianess for 16-bit instructions
are available in the git repository at:
git://github.com/drasko/openocd.git master
Drasko DRASKOVIC (4):
mips32: Removed Unnecessary JTAG Queue Flush
mips_m4k: common_magic should be unsigned
mips32: Added CP0 coprocessor R/W routines
mips32: Sync Caches to Make Instr Writes Effective
src/target/mips32.c | 106 ++++++++++++++
src/target/mips32.h | 117 ++++++++++++---
src/target/mips32_pracc.c | 342 +++++++++++++++++++++++++++++++++++++++++++--
src/target/mips32_pracc.h | 41 +++++-
src/target/mips_m4k.c | 108 ++++++++++++++-
src/target/mips_m4k.h | 7 +-
6 files changed, 679 insertions(+), 42 deletions(-)
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