Hi all, based on EJTAG spec, can somebody explain the difference between FASTDATA competition and not competition modes :
During a Fastdata access, the Fastdata register value shifted in specifies whether the Fastdata access should be completed or not. The value shifted out is a flag that indicates whether the Fastdata access was successful or not (if completion was requested). Shifting in a zero value requests completion of the Fastdata access. The PrAcc bit in the EJTAG Control register is overwritten with zero when the access succeeds. (The access succeeds if PrAcc is one and the operation address is in the legal dmseg segment Fastdata area.) When successful, a one is shifted out. Shifting out a zero indicates a Fastdata access failure. Shifting in a one does not complete the Fastdata access and the PrAcc bit is unchanged. Shifting out a one indicates that the access would have been successful if allowed to complete and a zero indicates the access would not have successfully completed. So my questions are : 1) If we demand completion, when do we do shift-out of the SPrAcc bit to check status : a) We shift in SPrAcc, we shift it out, we check it if it is "1" - that would say "You can send in data it will pass OK", and then we shift in data or b) We shift in SPrAcc, we shift in data, we shift out SPrAcc and check if if it is "1" - in this case check comes after data shift-in and it would say something like "Data shifted in were well written" ? Based on this : During Fastdata uploads and downloads, the processor will stall on accesses to the Fastdata area. The PrAcc (processor access pending bit) will be 1 indicating the probe is required to complete the access. Both upload and download accesses are attempted by shifting in a zero SPrAcc value (to request access completion) and shifting out SPrAcc to see if the attempt will be successful (i.e., there was an access pending and a legal Fastdata area address was used). Downloads will also shift in the data to be used to satisfy the load from the dmseg segment Fastdata area, while uploads will shift out the data being stored to the dmseg segment Fastdata area. I would say that it is case b) - pre-check SPrAcc and then shift-in data... But I am not sure. I do not know at which point to check. BR, Drasko _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
