Mathias K. wrote:
Hello,
Am 25.02.2011 14:38, schrieb Michael Schwingen:
Mathias K. wrote:
I think you can't simple abstract this with 8/16/24/32bit access, because in my
case the data bus
has always a 24bit width and the address bus increment is always one (one
address and 3 bytes of
data). There is no alternative alignment how you can describe a byte of this
24bit with a bus
address, thats the problem.
So the problem is that a word (of 24 bits) is supported as the *only* access
type?
Yes, thats true.
In that case, I think we should talk about unaligned accesses insteadof
harvard/risc.
Okay, sounds good.
Now the question is how to handle this at the higher layers:
- only allow word-sized accesses - ie. fail all byte-read/write attempts
This should work. GDB as example always read/write the memory or registers with
a 32bit access, the
highest byte is never used but transfered.
If all upper layers (including flash programming etc.) can live with
that restriction, this would be my preferred solution - do not try to
get smart and (badly) emulate things that the platform can't provide.
- invent virtual byte addresses (as word address * 3) and do read-modify-write
cycles in case a
single byte shall be written
This make the implementation very complicated and no difference to the outside.
I think thats not
the right way.
I agree - this sounds like a bad hack, but it might be necessary in case
other software that is much more difficult to change requires such a
behaviour.
So if it is only allowing/disallowing unaligned or non-machineword-sized
accesses, I think the chip driver should just provide 1 or 2 flags with
these meanings that the upper layers check. This is nothing the user
needs to change, right?
cu
Michael
cu
Michael
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