Hi All, I¹m working on a project that will require an ODM to program a NAND flash. I¹m providing 4 partitions worth of content to be programmed starting at 4 specific physical addresses on the chip. I understand from the ODM, that Hynix considers that up to 2% of the flash might be in bad blocks (in our case, ~80 128K blocks out of a 512M chip). Accounting for that is ok, but how much should be attributed to bad block density? Should I assume the worst case that the 2% bad blocks could possibly occur in each of the 4 partitions? That would mean that I would have to set aside +8% of the chip in 80 block buffers in each partition (partitions sizes are 1M,1M,4M,6M, rest of the chip). I was asking the ODM to ensure that no more than 2 bad blocks occur in any 4M range of the flash as a requirement. They are uncomfortable about that. Any other NAND booted device that I¹ve seen is not pessimistic about bad blocks being located in the same area and thus their flash partitioning seems optimistic.
Anyone have any place to get something official about bad block density? I suspect that in practice, 2 BB in 4M is reasonable and unlikely to cause issues, but without empirical documentation, I can¹t make a requirement. In a 512M NAND flash, setting aside +40M in sloppy partitioning seems very wasteful. Thoughts/Comments? Thanks, Robert -- Cisco 2200 E. Pres. George Bush Turnpike Richardson, TX 75082 jamwy...@cisco.com 972-813-1544 "Any sufficiently advanced technology is indistinguishable from magic" Arthur C. Clarke
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