On 23/12/2010 8.18, Øyvind Harboe wrote:
Apparently TI just did an A9 version of their BeagleBoard:
http://pandaboard.org/
Hi,
yes and I am one of the proud winners of it ;-)
You can find details of my "Panda Early Adopter Project" here (it
involves openocd as well):
http://pandaboard.org/content/porting-qi-bootlader-pandaboard
At the moment I'm trying to do some basic debugging on the board using
OpenOCD. I'm trying to do some modification to the Cortex A8 code to
adapt it to Cortex A9. I found a lot of difficulties due to lack of
documentation regarding the debug part of the MPU.
I'm also doing a bit of reverse engineering on the JTAG side.
What I've achieved for now is:
- configuring the DAP (it is at address 9 of JRC)
- reading/writing all the registers of the JTAG-DP
- reading some of the registers of the MEM-AP
My next steps will be:
- reading/writing to memory
- resetting the MPU
- halting MPU, entering debug state
- do some basic debugging (breakpoints, watchpoints)
If someone have some useful information regarding debug on Cortex-A9 it
would be very welcome.
In particular I would like to know:
- in Cortex-A8 (beagleboard), we have to write 0x00002000 to address
0x5401d030 to enable debug (DBGEN signal). Do I have to do something
similar in Cortex-A9?
- SRST is unavailable (TI-14 JTAG connector) on both Beagle and Panda.
On Cortex-A8, we have to write 0x2 to PRM_RSTCTRL (0x48307250) to cause
a warm reset. How can we achieve this on Cortex-A9?
- OMAP 4430 has two cores. Have someone experience on debugging
multicores (how to halt both cores? what happens when we stop only one
core? on the first phases of boot is sufficient to halt only the 1st MPU?)
Thank you in advance
Best regards
Luca Ellero
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