Hi all, I run into strange behavior with reset of my SoC. I am using "arm9 vector_catch reset" to catch the reset event from the button on the board, although "reset halt" gives the similar results, where I defined reset-assert procedure to write a byte in a SOC_RESET register. After executing the reset I am observing that some registers, especially "Clock gate enable" (for MII or AUX) registers are kept at 0x0, when correct reset value is 0x1 (i.e. enabled).
Doing the same reset with Lauterbach probe (and software) gives correct results, OK reset and good reset values for these registers, so I am suspecting that OpenOCD is not doing something correctly. This kind of behavior can be very dangerous, as the system software relays on correct reset values, and I have no idea what oter registers can be bad initialized by OpenOCD after reset. Did someone run into the similar problem and do you have any idea how this should be investigated. I appreciate any help or ideas. Kind regards, Drasko _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
