If I disable block writes, then the sequence below works fine. This is with a STM32F103ZEH6 and the default target/stm32.cfg script. The flash programming algorithm crashes with a "double fault".
Reducing WORKAREASIZE to 0x1000 did not help. reset halt flash probe 0 stm32x unlock 0 reset init flash erase_address 0x08000000 0x800 flash fillw 0x08000000 0x12345678 0x40 mdw 0x08000000 0x40 Simplest way to disable block writes is not to set aside any working memory: set WORKAREASIZE 0 source [find target/stm32.cfg] Debug: 724 147044 command.c:156 script_debug(): command - ocd_command ocd_command type ocd_flash fillw 0x08000000 0x12345678 0x40 Debug: 725 147044 command.c:156 script_debug(): command - ocd_flash ocd_flash fillw 0x08000000 0x12345678 0x40 Debug: 726 147044 log.c:438 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (1343). This may cause trouble with GDB connections. Debug: 729 147268 target.c:1632 target_write_u32(): address: 0x40022004, value: 0x45670123 Debug: 730 147396 target.c:1632 target_write_u32(): address: 0x40022004, value: 0xcdef89ab Debug: 731 147524 target.c:1128 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x20000000 Debug: 732 147524 target.c:1188 target_alloc_working_area_try(): allocated new working area at address 0x20000000 Debug: 733 147524 target.c:1318 target_write_buffer(): writing buffer of 48 byte at 0x20000000 Debug: 734 147656 target.c:1188 target_alloc_working_area_try(): allocated new working area at address 0x20000030 Debug: 735 147656 target.c:1318 target_write_buffer(): writing buffer of 256 byte at 0x20000030 Debug: 736 174066 armv7m.c:129 armv7m_restore_context(): Debug: 737 174548 cortex_m3.c:1585 cortex_m3_store_core_reg_u32(): write special reg 19 value 0x1 Debug: 738 174548 armv7m.c:239 armv7m_write_core_reg(): write core reg 19 value 0x1 Debug: 739 174804 cortex_m3.c:1551 cortex_m3_store_core_reg_u32(): write core reg 16 value 0x1000000 Debug: 740 174804 armv7m.c:239 armv7m_write_core_reg(): write core reg 16 value 0x1000000 Debug: 741 175060 cortex_m3.c:1551 cortex_m3_store_core_reg_u32(): write core reg 15 value 0x20000000 Debug: 742 175060 armv7m.c:239 armv7m_write_core_reg(): write core reg 15 value 0x20000000 Debug: 743 175321 cortex_m3.c:1551 cortex_m3_store_core_reg_u32(): write core reg 3 value 0x289408 Debug: 744 175321 armv7m.c:239 armv7m_write_core_reg(): write core reg 3 value 0x289408 Debug: 745 175576 cortex_m3.c:1551 cortex_m3_store_core_reg_u32(): write core reg 2 value 0x80 Debug: 746 175576 armv7m.c:239 armv7m_write_core_reg(): write core reg 2 value 0x80 Debug: 747 175834 cortex_m3.c:1551 cortex_m3_store_core_reg_u32(): write core reg 1 value 0x8000000 Debug: 748 175834 armv7m.c:239 armv7m_write_core_reg(): write core reg 1 value 0x8000000 Debug: 749 176092 cortex_m3.c:1551 cortex_m3_store_core_reg_u32(): write core reg 0 value 0x20000030 Debug: 750 176092 armv7m.c:239 armv7m_write_core_reg(): write core reg 0 value 0x20000030 Debug: 751 176221 target.c:1024 target_call_event_callbacks(): target event 22 (debug-resumed) Debug: 752 176221 cortex_m3.c:840 cortex_m3_resume(): target debug resumed at 0x20000000 Debug: 753 176348 target.c:2134 target_wait_state(): waiting for target halted... Debug: 754 176868 log.c:438 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (29824). This may cause trouble with GDB connections. Error: 761 179960 cortex_m3.c:542 cortex_m3_poll(): stm32.cpu -- clearing lockup after double fault Debug: 762 180216 cortex_m3.c:599 cortex_m3_poll(): Debug: 763 180217 cortex_m3.c:431 cortex_m3_debug_entry(): Debug: 764 180607 cortex_m3.c:172 cortex_m3_clear_halt(): NVIC_DFSR 0x1 Debug: 765 181005 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 0 value 0x20000030 Debug: 766 181261 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 1 value 0x8000000 Debug: 767 181524 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 2 value 0x80 Debug: 768 181780 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 3 value 0x289408 Debug: 769 182040 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 4 value 0x40022010 Debug: 770 182296 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 5 value 0x4002200c Debug: 771 182553 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 6 value 0x0 Debug: 772 182808 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 7 value 0x68000b10 Debug: 773 183064 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 8 value 0x0 Debug: 774 183323 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 9 value 0x0 Debug: 775 183580 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 10 value 0x0 Debug: 776 183839 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 11 value 0x68000b34 Debug: 777 184096 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 12 value 0x0 Debug: 778 184352 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 13 value 0xffffffdc Debug: 779 184609 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 14 value 0xfffffff9 Debug: 780 184869 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 15 value 0xfffffffe Debug: 781 185124 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 16 value 0x1000003 Debug: 782 185386 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 17 value 0xffffffdc Debug: 783 185644 cortex_m3.c:1473 cortex_m3_load_core_reg_u32(): load from core reg 18 value 0x68000b10 Debug: 784 185900 cortex_m3.c:1505 cortex_m3_load_core_reg_u32(): load from special reg 19 value 0x1 Debug: 785 186160 cortex_m3.c:1505 cortex_m3_load_core_reg_u32(): load from special reg 20 value 0x0 Debug: 786 186340 cortex_m3.c:1505 cortex_m3_load_core_reg_u32(): load from special reg 21 value 0x0 Debug: 787 186600 cortex_m3.c:1505 cortex_m3_load_core_reg_u32(): load from special reg 22 value 0x0 Debug: 788 186862 cortex_m3.c:398 cortex_m3_examine_exception_reason(): HardFault SHCSR 0x0, SR 0x40000000, CFSR 0x1, AR 0xffffffff Debug: 789 186862 cortex_m3.c:509 cortex_m3_debug_entry(): entered debug state in core mode: Handler at PC 0xfffffffe, target->state: halted Debug: 790 186862 target.c:1024 target_call_event_callbacks(): target event 21 (debug-halted) Debug: 791 186862 cortex_m3.c:630 cortex_m3_halt(): target->state: halted Debug: 792 186862 cortex_m3.c:634 cortex_m3_halt(): target was already halted Error: 793 186992 stm32x.c:582 stm32x_write_block(): error executing stm32x flash write algorithm Error: 794 186993 core.c:98 flash_driver_write(): error writing to flash at address 0x08000000 at offset 0x00000000 (-302) Debug: 795 186993 command.c:647 run_command(): Command failed with error code -302 User : 796 186993 command.c:688 command_run_line(): Command handler execution failed in procedure 'flash' -- Øyvind Harboe Can Zylin Consulting help on your project? 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