This patch introduces support for Cortex A8 based Freescale i.MX51 CPU. This CPU
has the Debug Access Port located at a different address (0x60008000) than TI
OMAP3 series of CPUs.
i.MX51 configuration file based on OMAP3 configuration file and an email from
Alan Carvalho de Assis <acas...@gmail.com>.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
---
src/target/cortex_a8.c | 7 ++++-
tcl/target/imx51.cfg | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+), 2 deletions(-)
create mode 100644 tcl/target/imx51.cfg
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 64b78bd..3fe9c4b 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -73,7 +73,8 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t
*result);
*/
#define swjdp_memoryap 0
#define swjdp_debugap 1
-#define OMAP3530_DEBUG_BASE 0x54011000
+#define OMAP3530_DEBUG_BASE 0x54011000
+#define IMX51_DEBUG_BASE 0x60008000
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
@@ -1719,7 +1720,9 @@ static int cortex_a8_examine_first(struct target *target)
LOG_DEBUG("TODO - autoconfigure");
/* Here we shall insert a proper ROM Table scan */
- if (strcmp(target->variant, "amdm37x") == 0)
+ if (strcmp(target->variant, "imx51") == 0)
+ armv7a->debug_base = IMX51_DEBUG_BASE;
+ else if (strcmp(target->variant, "amdm37x") == 0)
armv7a->debug_base = OMAP3530_DEBUG_BASE;
else if (strcmp(target->variant, "omap3530") == 0)
armv7a->debug_base = OMAP3530_DEBUG_BASE;
diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg
new file mode 100644
index 0000000..35d8a2c
--- /dev/null
+++ b/tcl/target/imx51.cfg
@@ -0,0 +1,52 @@
+# Freescale i.MX51
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imx51
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID ] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x1ba00477
+}
+
+jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
+
+# SJC
+if { [info exists SJC_TAPID ] } {
+ set _SJC_TAPID SJC_TAPID
+} else {
+ set _SJC_TAPID 0x0190c01d
+}
+
+jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
+ -expected-id $_SJC_TAPID -ignore-version
+
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP \
+ -variant imx51
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
+
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
+
+proc imx51_dbginit {target} {
+ # General Cortex A8 debug initialisation
+ cortex_a8 dbginit
+}
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"
--
1.7.1
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