Hi Laurant, > Great job.
Far from done though. I mainly get zeroes at the moment, because my chip continues to run. I'm still looking for the right incantation to make it stop. > This is true for some specific processors. But wrong for CPLD , FPGA, > ...., and some ARM having methods to select Boundary Scan or internal > Debug via external pin setup ... Thanks, I made a change. Note however, the docs are as premature as the code. > If you want to indirect Flash a memory over JTAG Boundary Scan from a > FPGA, you only need TCK TMS TDI TDO JTAG Signals:-) ! If you have a general recipe, I'm interested. But if it differs between FPGA types/brands I won't add it in this code. I'm not even sure at this point if the principle I'm aiming at can actually be made to work in general -- this is my first JTAG project. Thanks, -Rick _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
