I've been trying to use OpenOCD with the STM32F100C4T6B, one of the new "low density value line" processors from STMicroelectronics.
I haven't had too much success using it (not stopping at breakpoints, not noticing when it has stopped at breakpoints, not working well with gdb, not stepping once at a breakpoint, etc.) and I was thinking that this information from the errata sheet might have something to do with my problems. Could anyone tell me whether this silicon bug will affect OpenOCD, and, if so, how? 2.5 Boundary scan TAP: wrong pattern sent out after the “capture IR” state Description After the “capture IR” state of the boundary scan TAP, the two least significant bits in the instruction register should be loaded with “01” for them to be shifted out whenever a next instruction is shifted in. However, the boundary scan TAP shifts out the latest value loaded into the instruction register, which could be “00”, “01”, “10” or “11”. Workaround The data shifted out, after the capture IR state, in the boundary scan flow should therefore be ignored and the software should check not only the two least significant bits (XXX01) but all register bits (XXXXX). Thanks, Ned Konz _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
