Hi Mike, On Wed, Sep 15, 2010 at 5:23 PM, Mike Dunn <miked...@newsguy.com> wrote: > This is odd. I am using OpenOCD on a pxa270 target and I don't see this, > neither through telnet nor gdb. Assumed this was a cache-related problem on > arm946. Might be... But I introduced cache-flushing on memory write in OPenOCD code, as I explained before, and the problem persist.
Can somebody confirm that this : https://lists.berlios.de/pipermail/openocd-development/2010-September/016401.html is a correct procedure to flush the caches (I am using arm966e as a target, but have arm946e core in my chip), i.e. based on information given here : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.arm9/index.html would these lines : printf ("Invalidate I$\n"); retval = arm966e_write_cp15(target, 0x0f, 0); printf ("Invalidate D$\n"); retval = arm966e_write_cp15(target, 0x0e, 0); really flush the cache ? If somebody can confirm this, than we can sign-off cache coherency as a problem and concentrate on a breakpoint handling. > > Drasko, I looked at breakpoint management recently. It's not that arcane, > though the call stack is a bit long; mostly wrapper functions: > > handle_bp_command() -> handle_bp_command_set() -> breakpoint_add() -> > target_add_breakpoint() > -> <arch>_add_breakpoint -> <arch>_set_breakpoint() > > Most of the infrastructure code is in breakpoint_add(), which allocates and > populates a structure to record the breakpoint, and of course > <arch>_set_breakpoint(). Thanks Mike, I will have a look at this. BR, Drasko _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
