> eval "bar $args"
And we have a winner!! Thank you!!!
I think the docs which described $args to me
somehow omitted the fact that it was an
array, that'd need "eval" in this routine
varargs scenario...
Attached is the updated patch. I'm calling it
SWD infrastructure patch #1, with the second
being the one with SWD transport support and the
driver hooks. I'll want to commit this one first
since it's (now!) innocuous ... and will send the
second along after I make sure it interacts right
with my driver patch. That way it'll be easier for
other folk (like Simon) to add their contributions
to an upcoming SWD-fest ... :) I still see debug
adapter driver support coming last (before tuning
and lots of fiddling).
Once this does get committed, it should be easy to
teach other SWJ-DP based hardware how to not care
what transport is in use. STM32 being the only one
with much complication (since it's got a separate JTAG TAP for boundary scan,
which really ought to
get declared -- iff JTAG is in use not SWD.
From: David Brownell <dbrown...@users.sourceforge.net>
Subject: swj-dp.tcl (SWD infrastructure #1)
Provide new helper proc that can set up either an SWD or JTAG DAP
based on the transport which is in use -- mostly for SWJ-DP.
Also update some SWJ-DP based chips/targets to use it. The goal
is making SWD-vs-JTAG transparent in most places. SWJ-DP based chips
really need this flexible configuration to cope with debug adapters
that support different transports, without needing new target configs
for each transport.
For JTAG-DP, callers will use "jtag newtap" directly, as today; only
one chip-level transport option exists.
For SW-DP (e.g. LPC11xx or LPC13xx, they'll use "swd newdap" directly
(part of an upcoming SWD transport patch). Again, only one transport
option exists, so hard-wiring is appropriate there.
Signed-off-by: David Brownell <dbrown...@users.sourceforge.net>
---
tcl/target/lpc1768.cfg | 7 ++++++-
tcl/target/stellaris.cfg | 17 ++++++++++++++++-
tcl/target/swj-dp.tcl | 25 +++++++++++++++++++++++++
3 files changed, 47 insertions(+), 2 deletions(-)
--- /dev/null
+++ oocd/tcl/target/swj-dp.tcl
@@ -0,0 +1,25 @@
+# ARM Debug Interface V5 (ADI_V5) utility
+# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
+# SW-DP and JTAG-DP targets don't need to switch based
+# on which transport is active.
+#
+# declare a JTAG or SWD Debug Access Point (DAP)
+# based on the transport in use with this session.
+# You can't access JTAG ops when SWD is active, etc.
+
+# params are currently what "jtag newtap" uses
+# because OpenOCD internals are still strongly biased
+# to JTAG .... but for SWD, "irlen" etc are ignored,
+# and the internals work differently
+
+# for now, ignore non-JTAG and non-SWD transports
+# (e.g. initial flash programming via SPI or UART)
+
+# split out "chip" and "tag" so we can someday handle
+# them more uniformly irlen too...)
+
+proc swj_newdap {chip tag args} {
+set tran [transport select]
+if [string equal $tran "jtag"] { eval jtag newtap $chip $tag $args}
+if [string equal $tran "swd"] { eval swd newdap $chip $tag $args }
+}
--- oocd.orig/tcl/target/stellaris.cfg
+++ oocd/tcl/target/stellaris.cfg
@@ -1,5 +1,12 @@
# TI/Luminary Stellaris LM3S chip family
+# Luminary chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# For now we ignore the SPI and UART options, which
+# are usable only for ISP style initial flash programming.
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@@ -18,9 +25,17 @@ if { [info exists CPUTAPID ] } {
set _CPUTAPID 0x0ba00477
}
-jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+# SWD DAP, and JTAG TAP, take same params for now;
+# ... even though SWD ignores all except TAPID, and
+# JTAG shouldn't need anything more then irlen.
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-expected-id $_CPUTAPID -ignore-version
+#jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+# -expected-id $_CPUTAPID -ignore-version
+
+
# The "lm3s" variant uses a software reset rather than SRST.
# This stops the debug registers from being cleared; it works
# around an erratum which should be fixed in later silicon.
--- oocd.orig/tcl/target/lpc1768.cfg
+++ oocd/tcl/target/lpc1768.cfg
@@ -1,5 +1,9 @@
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+# LPC17xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@@ -31,7 +35,8 @@ jtag_ntrst_delay 200
# LPC2000 & LPC1700 -> SRST causes TRST
reset_config srst_pulls_trst
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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