I made a fleeting vain attempt setting up the vector
catch register to halt upon reset.
Attached is the code that I wrote to set up the vector
catch register to catch reset(I gleaned at the ARM11
code for this + read a bit in the Cortex A8 manual).
No luck, at least with the TI AM3517 EVM target.
I've got the probe connected to the JTAG 20, but when
I tried with SRST reset instead of using the reset-assert
event(see board/am3517evm.cfg), then it seemed
like communication broke down completely with the
target(lots of sticky errors, etc.).
--
Øyvind Harboe
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index afe5b6c..5b83a9a 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1289,10 +1289,22 @@ static int cortex_a8_remove_breakpoint(struct target
*target, struct breakpoint
static int cortex_a8_assert_reset(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
-
+ struct adiv5_dap *swjdp = &armv7a->dap;
+ int retval;
LOG_DEBUG(" ");
- /* FIXME when halt is requested, make it work somehow... */
+ /* See Cortex-A8 Technical Reference Manual 12.4.8 Vector Catch
Register */
+ if (target->reset_halt)
+ {
+ uint32_t vcr;
+ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base +
CPUDBG_VCR, &vcr);
+ if (retval != ERROR_OK)
+ return retval;
+ vcr |= 1;
+ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base +
CPUDBG_VCR, vcr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
/* Issue some kind of warm reset. */
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
@@ -1318,6 +1330,8 @@ static int cortex_a8_assert_reset(struct target *target)
static int cortex_a8_deassert_reset(struct target *target)
{
int retval;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
LOG_DEBUG(" ");
@@ -1329,6 +1343,16 @@ static int cortex_a8_deassert_reset(struct target
*target)
return retval;
if (target->reset_halt) {
+ /* See Cortex-A8 Technical Reference Manual 12.4.8 Vector Catch
Register */
+ uint32_t vcr;
+ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base +
CPUDBG_VCR, &vcr);
+ if (retval != ERROR_OK)
+ return retval;
+ vcr &= ~1;
+ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base +
CPUDBG_VCR, vcr);
+ if (retval != ERROR_OK)
+ return retval;
+
if (target->state != TARGET_HALTED) {
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
_______________________________________________
Openocd-development mailing list
Openocd-development@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/openocd-development
