Spencer Oliver 写道:
On 02/06/2010 09:24, Xiaochen Zhou wrote:
Hi all,
I want to port eCos to an epon onu chip which has a MIPS 4KEc core and
using openocd v0.4.0 + wiggler for debugging. Gdb seems ok(ctrl_c and
continue commands ok) but breakpoint.
Just a guess but unless you have a valid flash memory map then gdb
will assume ram breakpoints for the break cmd.
If this is not the case then use the following openocd cmd to set all
breakpoints as hardware, or use hbreak instead.
gdb_breakpoint_override hard
Cheers
Spen
It seems some issues in openocd-0.4.0 with MIPS 4KEc core, I did some
experiments below:
Issue 1:
In telnet console, I set the breakpoint at 0x80000000, when I dump
memory in uboot, the SDBBP(software debug breakpoint) in memory is
0x3F000070 not 0x7000003F, so it's endian issue.
I modify src/target/mips32.h
line 138: #define MIPS32_SDBBP 0x7000003F ------> #define MIPS32_SDBBP
0x3F000070
then it's ok in uboot memory dump.
Issue 2:
In last mail, the software breakpoint can not been trigged. I dump
memory in uboot in address 0x80000000 and 0xA0000000, the content is
different. Because uboot boot with cache attribute is "write-back", it's
the key point. I initialize eCos cache with "write-through", software
breakpoint can trigged in my eCos App.
Issue 3:
When eCos App is trigged by software breakpoint, I clear the breakpoint
and hit the 'c' in gdb, the app is trigged again , and the stopped
address is same as the breakpoint which I had setted and cleared. I dump
the address in the openocd telnet console, the memory has changed from
SDBBP to original instrument. I initialize eCos with cache disabled, gdb
run ok. I think, when openocd recover the original instrument, it maybe
forget to invalidate the instrument cache.
I'm not familiar with openocd, can any expert in list review this and
confirm these issues?
Here is my entironment:
MIPS 4KEc
Big_endian
running eCos v3.0 without MMU
toolchain: gcc version 3.2.1 (eCosCentric)
Thanks
Xiaochen Zhou
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