On Thursday 11 February 2010 15:47:24 Øyvind Harboe wrote:
> On Thu, Feb 11, 2010 at 3:37 PM, Marc Pignat <marc.pig...@hevs.ch> wrote:
> > On Thursday 11 February 2010 15:10:12 Øyvind Harboe wrote:
> >> Backing out that change, will break non-MMU execution. Baaad....
> >>
> >> I tried to copy & paste the solution from 926ejs which also supports
> >> writing breakpoints to memory marked as read only by the MMU.
> >> Bonus!
> >>
> >> I don't have hardware to test on.
> >>
> >> If it works it fixes a bug as well as adds a new feature.
> >
> > Error: arm920_virt2phys: not implemented
> >
> >
> > I tried to copy virtphys from 926ejs, the debugged software still crashes.
> >
> > What do you think about flushing the write buffer after flushing the data
> > cache?
>
> We're still short the feature of stepping through read only code in
> RAM....
>
> I'd rather see virt2phys added to arm920
I don't know if this info is useful, but when disabling the data cache flush,
the
debugged software does not crash!
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e0b1c70..eb2cfff 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -524,7 +524,7 @@ int arm920t_write_memory(struct target *target, uint32_t
address, uint32_t size,
if (((size == 4) || (size == 2)) && (count == 1))
{
struct arm920t_common *arm920t = target_to_arm920(target);
-
+#if 0
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
LOG_DEBUG("D-Cache enabled, flush and invalidate cache
line");
@@ -533,7 +533,7 @@ int arm920t_write_memory(struct target *target, uint32_t
address, uint32_t size,
if (retval != ERROR_OK)
return retval;
}
-
+#endif
if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{
LOG_DEBUG("I-Cache enabled, invalidating affected
I-Cache line");
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