How's this?
--
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
From 828d006a9d05b24b6dcdf1c552912e04586d6f7d Mon Sep 17 00:00:00 2001
From: =?utf-8?q?=C3=98yvind=20Harboe?= <oyvind.har...@zylin.com>
Date: Mon, 23 Nov 2009 18:23:10 +0100
Subject: [PATCH] arm926ejs: fix gaffe when converting from arm926ejs cp15 to mcr
MIME-Version: 1.0
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the first arg is the register number 15 = cp15.
Signed-off-by: Øyvind Harboe <oyvind.har...@zylin.com>
---
tcl/board/dm355evm.cfg | 2 +-
tcl/board/openrd.cfg | 2 +-
tcl/board/sheevaplug.cfg | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 2e298b7..2c8bea8 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -182,7 +182,7 @@ proc dm355evm_init {} {
########################
# turn on icache - set I bit in cp15 register c1
- mcr 0 0 1 0 0x00051078
+ mcr 15 0 0 1 0 0x00051078
}
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index 4bc708d..12cc79e 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -29,7 +29,7 @@ proc openrd_init { } {
jtag_reset 0 0
wait_halt
- mcr 0 0 1 0 0x00052078
+ mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index 8e8396d..9267eb9 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -29,7 +29,7 @@ proc sheevaplug_init { } {
jtag_reset 0 0
wait_halt
- mcr 0 0 1 0 0x00052078
+ mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register
--
1.6.3.3
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