> Sadly, that also requires a lot of engineering expertise to write that
Actually the hardware description is not as bad as you might first think, I have a prototype Xilinx CoolRunnerII CPLD hooked up to a Cypress high speed FX2, this effectively gives a direct pipe from the OpenOCD USB calls to the CPLD (via the FX2 slave interface). I'm a software engineer and selected this challenge as a first project to teach myself Verilog, it's really just a simple state machine with a few twiddles. My long term plan is to make all of this open source including: board design, verilog code, FX2 firmware and the Openocd patch... It is very prototype at the moment, currently it implements the SCANIO in hardware everything else is still bit banged but it does work. Liam. ----- Original Message ----- From: "Duane Ellis" <open...@duaneellis.com> To: "Openocd-Dev" <openocd-development@lists.berlios.de> Sent: Saturday, November 21, 2009 3:42 PM Subject: [Openocd-development] Openocd vrs Commercial jtag dongles > Recently, I've been using quite a few commercial jtag tools from chip > vendors. > > One thing I've noticed is that they all have implement the design with > an small usb-controller + FPGA of some type (typically a xilinx > spartan). I can see the real benefit, they download and flash the target > at an unbelievable speed, ie: couple seconds for 256K of data. In > contrast, non-fpga solutions, (bitbang & ftdi, etc) are much slower > overall. > > My guess is they are creating a hugely fast chip specific download > engine they just feed data bytes to - and it operates at some hugely > fast speed (that probably helps) In theory, the dongle has 2 modes, > "simple slow bitbang" - once the target is determined, download an > acceleration engine the fpga. > > The debugger step-in/over/line/etc rate with these tools is so fast... > perhaps they have have implemented some common tasks like step and > register dump type sequences in the dongle's fpga. Watch windows are > for example very snappy. > > Sadly, that also requires a lot of engineering expertise to write that > fpga code. in the cases I've seen [ie: vendor supplied tools] the chip > companies also have a large pool of people who know or understand > verilog/vhdl and can write such fpga code. > > It is just blindingly fast... > > -Duane. > > > > > > _______________________________________________ > Openocd-development mailing list > Openocd-development@lists.berlios.de > https://lists.berlios.de/mailman/listinfo/openocd-development > _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
