Hi,
I have just tested OpenOCD 0.3.1 with a StorLink SL3516 (Gemini) SoC.
This SoC contains a FA526 ARM CPU core and all the peripherials needed
for NAS, Router, and similar applications. (The system is an
IB-NAS4220-B which fortunately has a 20-pin JTAG on its mainboard.)
The problem:
The pc displayed contains the value of the just executed instruction.
Consider the following OpenOCD session:
> armv4_5 disassemble 0 32
0x00000000 0xea000012 B 0x00000050
0x00000004 0xe59ff018 LDR r15, [r15, #0x18]
0x00000008 0xe59ff018 LDR r15, [r15, #0x18]
0x0000000c 0xe59ff018 LDR r15, [r15, #0x18]
0x00000010 0xe59ff018 LDR r15, [r15, #0x18]
0x00000014 0xea00000d B 0x00000050
0x00000018 0xe59ff018 LDR r15, [r15, #0x18]
0x0000001c 0xe59ff018 LDR r15, [r15, #0x18]
0x00000020 0x00000050 ANDEQ r0, r0, r0, ASR r0
0x00000024 0x00000418 ANDEQ r0, r0, r8, LSL r4
0x00000028 0x00000418 ANDEQ r0, r0, r8, LSL r4
0x0000002c 0x00000418 ANDEQ r0, r0, r8, LSL r4
0x00000030 0x00000418 ANDEQ r0, r0, r8, LSL r4
0x00000034 0x00000000 ANDEQ r0, r0, r0
0x00000038 0x00000420 ANDEQ r0, r0, r0, LSR #0x8
0x0000003c 0x00000418 ANDEQ r0, r0, r8, LSL r4
0x00000040 0x6500000c STRVS r0, [r0, #-0xc]
0x00000044 0x30000200 ANDCC r0, r0, r0, LSL #0x4
0x00000048 0x30000800 ANDCC r0, r0, r0, LSL #0x10
0x0000004c 0x40000030 ANDMI r0, r0, r0, LSR r0
0x00000050 0xe3a000d3 MOV r0, #0xd3
0x00000054 0xe129f000 MSR CPSR_cf, r0
0x00000058 0xe59f0434 LDR r0, [r15, #0x434]
0x0000005c 0xe3a01000 MOV r1, #0x0
0x00000060 0xe5801000 STR r1, [r0]
0x00000064 0xe24f002c SUB r0, r15, #0x2c
0x00000068 0xe5901000 LDR r1, [r0]
0x0000006c 0xe5911000 LDR r1, [r1]
0x00000070 0xe2012b06 AND r2, r1, #0x1800
0x00000074 0xe3520000 CMP r2, #0x0
0x00000078 0x1a000004 BNE 0x00000090
0x0000007c 0xe3a001c1 MOV r0, #0x40000030
> bp 0x00000054 4 hw
breakpoint set at 0x00000054
resume
[reboot by bootloader]
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000050
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> armv4_5 reg
r0: 000000d3 r0: 000000d3 r0: 000000d3 r0:
000000d3 r0: 000000d3 r0: 000000d3
r1: 00000000 r1: 00000000 r1: 00000000 r1:
00000000 r1: 00000000 r1: 00000000
...
pc: 00000050 pc: 00000050 pc: 00000050 pc:
00000050 pc: 00000050 pc: 00000050
cpsr: 000000d3 spsr_fiq: 00000010 spsr_irq: 80000013 spsr_svc:
00000011 spsr_abt: 00000010 spsr_und: 00000090
[The instruction at address 0x00000050 was executed.]
> step
target state: halted
target halted in ARM state due to single-step, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000050
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> step
target state: halted
target halted in ARM state due to single-step, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000050
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> rbp 0x00000054
[The breakpoint must be removed to step further.]
> step
target state: halted
target halted in ARM state due to single-step, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000054
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Regards,
Peter
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