Now, without line breaks
----------------------
Common target file for LM3S CPU family
Signed-off-by: Yegor Yefremov <yegorsli...@googlemail.com>
Index: openocd/tcl/target/luminary.cfg
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ openocd/tcl/target/luminary.cfg 2009-11-09 09:57:02.000000000 +0100
@@ -0,0 +1,36 @@
+# TI/Luminary Stellaris LM3S CPU Family
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x3ba00477
+}
+
+# jtag speed
+jtag_khz 500
+
+#jtag scan chain
+# CPU TAP ID 0x1ba00477 for lm3s811 first revision added
+# CPU TAP ID 0x2ba00477 for lm3s811 Rev C2 added
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf
-expected-id 0x1ba00477 -expected-id 0x2ba00477 -expected-id
$_CPUTAPID
+
+# the luminary variant causes a software reset rather than asserting SRST
+# this stops the debug registers from being cleared
+# this will be fixed in later revisions of silicon
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
-variant lm3s
+
+# 16k working area at base of ram, not backed up
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
0x4000 -event reset-init {jtag_khz 3000}
+
+#flash configuration
+flash bank stellaris 0 0 0 0 $_TARGETNAME
+
+
+
On Mon, Nov 9, 2009 at 10:23 AM, Yegor Yefremov
<yegorsli...@googlemail.com> wrote:
> Common target file for LM3S CPU family
>
> Signed-off-by: Yegor Yefremov <yegorsli...@googlemail.com>
>
> Index: openocd/tcl/target/luminary.cfg
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ openocd/tcl/target/luminary.cfg 2009-11-09 09:57:02.000000000 +0100
> @@ -0,0 +1,36 @@
> +# TI/Luminary Stellaris LM3S CPU Family
> +
> +if { [info exists CHIPNAME] } {
> + set _CHIPNAME $CHIPNAME
> +} else {
> + set _CHIPNAME lm3s
> +}
> +
> +if { [info exists CPUTAPID ] } {
> + set _CPUTAPID $CPUTAPID
> +} else {
> + set _CPUTAPID 0x3ba00477
> +}
> +
> +# jtag speed
> +jtag_khz 500
> +
> +#jtag scan chain
> +# CPU TAP ID 0x1ba00477 for lm3s811 first revision added
> +# CPU TAP ID 0x2ba00477 for lm3s811 Rev C2 added
> +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf
> -expected-id 0x1ba00477 -expected-id 0x2ba00477 -expected-id
> $_CPUTAPID
> +
> +# the luminary variant causes a software reset rather than asserting SRST
> +# this stops the debug registers from being cleared
> +# this will be fixed in later revisions of silicon
> +set _TARGETNAME $_CHIPNAME.cpu
> +target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
> -variant lm3s
> +
> +# 16k working area at base of ram, not backed up
> +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
> 0x4000 -event reset-init {jtag_khz 3000}
> +
> +#flash configuration
> +flash bank stellaris 0 0 0 0 $_TARGETNAME
> +
>
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