In arm920t_write_memory, how about imitate arm926ejs_write_memory?
if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) ||
(size==4)))
{
/* special case the handling of single word writes to bypass MMU
* to allow implementation of breakpoints in memory marked read only
* by MMU */
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
/* MCR p15,0,Rd,c7,c10,2 */
retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0,
address);
if (retval != ERROR_OK)
return retval;
}
uint32_t pa, cb, ap;
int type, domain;
pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
address, &type, &cb, &domain, &ap);
if (type == -1)
return ERROR_OK;
/* cacheable & bufferable means write-back region */
if (cb == 3)
armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
pa, size, count, buffer);
} else
{
if ((retval = arm7_9_write_memory(target, address, size, count,
buffer)) != ERROR_OK)
return retval;
}
About I-cache, should arm920t follows arm926ejs ?
if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{
if (count <= 1)
{
/* invalidate ICache single entry with MVA */
arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
}
else
{
/* invalidate ICache */
arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
}
}
2009/11/3 Øyvind Harboe <oyvind.har...@zylin.com>
> On Tue, Nov 3, 2009 at 2:15 PM, Dennis.Cheng <m8939...@gmail.com> wrote:
> > Thanks. It works well :-).
>
> I've pushed the fix.
>
> I'm a little bit worried about being able to test the case where
> a write to a cache line for a breakpoint.
>
> Here the code has to flush that cache line + invalidate the cache line.
>
>
> --
> Øyvind Harboe
> http://www.zylin.com/zy1000.html
> ARM7 ARM9 ARM11 XScale Cortex
> JTAG debugger and flash programmer
>
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