Updates that make the reset work on these boards. Please update to the
svn tree.
# board(-config) specfic parameters file.
# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
proc config {label} {
return [dict get [configC100] $label ]
}
# show the value for the param. with label
proc showconfig {label} {
puts [format "0x%x" [dict get [configC100] $label ]]
}
# Telo board config
# when there are more then one board config
# use soft links to c100board-config.tcl
# so that only the right board-config gets
# included (just like include/configs/board-configs.h
# in u-boot.
proc configC100 {} {
# xtal freq. 24MHz
dict set configC100 CFG_REFCLKFREQ 24000000
# Amba Clk 165MHz
dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000
dict set configC100 w_amba 1
dict set configC100 x_amba 1
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
# Arm Clk 450MHz, must be a multiple of 25 MHz
dict set configC100 CFG_ARM_CLOCK 450000000
dict set configC100 w_arm 0
dict set configC100 x_arm 1
# y = arm_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
}
# This should be called for reset init event handler
proc setupTelo {} {
# setup GPIO used as control signals for C100
setupGPIO
# This will allow acces to lower 8MB or NOR
lowGPIO5
# setup NOR size,timing,etc.
setupNOR
# setup internals + PLL + DDR2
initC100
}
proc setupNOR {} {
puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
# enable Expansion Bus Clock + CS0 (NOR)
mww $EX_CSEN_REG 0x3
# set the address space for CS0=16MB
mww $EX_CS0_SEG_REG 0x7ff
# set the CS0 bus width to 16-bit
mww $EX_CS0_CFG_REG 0x202
# set timings to NOR
mww $EX_CS0_TMG1_REG 0x03034006
mww $EX_CS0_TMG2_REG 0x04040002
#mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
# everthing else is OK with default
}
proc bootNOR {} {
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
set DDR_RST [regs DDR_RST]
# put DDR controller in reset (so that it comes reset in u-boot)
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
# setup CS0 controller for NOR
setupNOR
# make sure we are accessing the lower part of NOR
lowGPIO5
# set PC to start of NOR (at boot 0x20000000 = 0x0)
reg pc $EXP_CS0_BASEADDR
# run
resume
}
proc setupGPIO {} {
puts "Setting up GPIO block for Telo"
# This is current setup for Telo (see sch. for details):
#GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
#GPIO1 irq line for FXS-FXO
#GPIO5 addr22 for NOR flash (access to upper 8MB)
#GPIO17 reset for DECT module.
#GPIO29 CS_n for NAND
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
set GPIO_OE_REG [regs GPIO_OE_REG]
# set GPIO29=GPIO17=1, GPIO5=0
mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
# enable [as output] GPIO29,GPIO17,GPIO5
mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5]
}
proc highGPIO5 {} {
puts "GPIO5 high"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=1
mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
}
proc lowGPIO5 {} {
puts "GPIO5 low"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=0
mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
}
proc boardID {id} {
# so far built:
# 4'b1111
dict set boardID 15 name "EVT1"
dict set boardID 15 ddr2size 128M
# dict set boardID 15 nandsize 1G
# dict set boardID 15 norsize 16M
# 4'b0000
dict set boardID 0 name "EVT2"
dict set boardID 0 ddr2size 128M
# 4'b0001
dict set boardID 1 name "EVT3"
dict set boardID 1 ddr2size 256M
# 4'b1110
dict set boardID 14 name "EVT3_old"
dict set boardID 14 ddr2size 128M
# 4'b0010
dict set boardID 2 name "EVT4"
dict set boardID 2 ddr2size 256M
return $boardID
}
# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
proc ooma_board_detect {} {
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
# read the current value of the BOOTSRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
# extract the GPBP bits
set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
# display board ID
puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
# show it on serial console
putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
# return the ddr2 size, used to configure DDR2 on a given board.
return [dict get [boardID $gpbt] $gpbt ddr2size]
}
proc configureDDR2regs_256M {} {
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
set DENALI_CTL_02_VAL 0x0100000000010100
set DENALI_CTL_11_VAL 0x433a32164a560a00
mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
# 01_DATA mod [40]=1, enable BA2
mw64bit $DENALI_CTL_01_DATA 0x0100010100000001
mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
mw64bit $DENALI_CTL_04_DATA 0x0000010100000001
mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
mw64bit $DENALI_CTL_06_DATA 0x060a020200020202
mw64bit $DENALI_CTL_07_DATA 0x0000000300000206
mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209
mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a
mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18
# 11_DATA mod [39-32]=16,more refresh
mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
mw64bit $DENALI_CTL_12_DATA 0x0000000000000800
mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000
mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000
mw64bit $DENALI_CTL_17_DATA 0x0000000000000000
mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600
mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8
set wr_dqs_shift 0x40
# start DDRC
mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
# wait int_status[2] (DRAM init complete)
puts -nonewline "Waiting for DDR2 controller to init..."
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
while { [expr $tmp & 0x040000] == 0 } {
sleep 1
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
}
puts "done."
# do ddr2 training sequence
# TBD (for now, if you need it, run trainDDR command)
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
# The values are computed based on Mindspeed and Nanya datasheets
proc configureDDR2regs_128M {} {
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
set DENALI_CTL_02_VAL 0x0100010000010100
set DENALI_CTL_11_VAL 0x433A42124A650A37
# set some default values
mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
mw64bit $DENALI_CTL_04_DATA 0x0201010100000201
mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
mw64bit $DENALI_CTL_06_DATA 0x050A020200020202
mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205
mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209
mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00
mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A
mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
mw64bit $DENALI_CTL_12_DATA 0x0000080000000800
mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
mw64bit $DENALI_CTL_15_DATA 0x0508000000000000
mw64bit $DENALI_CTL_16_DATA 0x000020472D200000
mw64bit $DENALI_CTL_17_DATA 0x0000000008000000
mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604
mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8
set wr_dqs_shift 0x40
# start DDRC
mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
# wait int_status[2] (DRAM init complete)
puts -nonewline "Waiting for DDR2 controller to init..."
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
while { [expr $tmp & 0x040000] == 0 } {
sleep 1
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
}
# This is not necessary
#mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
puts "done."
# do ddr2 training sequence
# TBD (for now, if you need it, run trainDDR command)
}
proc setupUART0 {} {
# configure UART0 to 115200, 8N1
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
set UART0_LCR [regs UART0_LCR]
set LCR_DLAB [regs LCR_DLAB]
set UART0_DLL [regs UART0_DLL]
set UART0_DLH [regs UART0_DLH]
set UART0_IIR [regs UART0_IIR]
set UART0_IER [regs UART0_IER]
set LCR_ONE_STOP [regs LCR_ONE_STOP]
set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
set FCR_XMITRES [regs FCR_XMITRES]
set FCR_RCVRRES [regs FCR_RCVRRES]
set FCR_FIFOEN [regs FCR_FIFOEN]
set IER_UUE [regs IER_UUE]
# unlock writing to IOCTRL register
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
# enable UART0
mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
# baudrate 115200
# This should really be amba_clk/(16*115200) but amba_clk=165MHz
set tmp 89
# Enable Divisor Latch access
mmw $UART0_LCR $LCR_DLAB 0x0
# set the divisor to $tmp
mww $UART0_DLL [expr $tmp & 0xff]
mww $UART0_DLH [expr $tmp >> 8]
# Disable Divisor Latch access
mmw $UART0_LCR 0x0 $LCR_DLAB
# set the UART to 8N1
mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
# reset FIFO
mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
# enable FFUART
mww $UART0_IER $IER_UUE
}
proc putcUART0 {char} {
set UART0_LSR [regs UART0_LSR]
set UART0_THR [regs UART0_THR]
set LSR_TEMT [regs LSR_TEMT]
# convert the 'char' to digit
set tmp [ scan $char %c ]
# /* wait for room in the tx FIFO on FFUART */
while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
mww $UART0_THR $tmp
if { $char == "\n" } { putcUART0 \r }
}
proc putsUART0 {str} {
set index 0
set len [string length $str]
while { $index < $len } {
putcUART0 [string index $str $index]
set index [expr $index + 1]
}
}
proc trainDDR2 {} {
set ARAM_BASEADDR [regs ARAM_BASEADDR]
# you must have run 'reset init' or u-boot
# load the training code to ARAM
load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
# set PC to start of NOR (at boot 0x20000000 = 0x0)
reg pc $ARAM_BASEADDR
# run
resume
}
proc flashUBOOT {file} {
# this will update uboot on NOR partition
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
# setup CS0 controller for NOR
setupNOR
# make sure we are accessing the lower part of NOR
lowGPIO5
flash probe 0
puts "Erasing sectors 0-3 for uboot"
putsUART0 "Erasing sectors 0-3 for uboot\n"
flash erase_sector 0 0 3
puts "Programming u-boot"
putsUART0 "Programming u-boot..."
memwrite burst enable
flash write_image $file $EXP_CS0_BASEADDR
memwrite burst disable
putsUART0 "done.\n"
putsUART0 "Rebooting, please wait!\n"
reboot
}
proc helpC100 {} {
puts "List of useful functions for C100 processor:"
puts "1) reset init: will set up your Telo board"
puts "2) setupNOR: will setup NOR access"
puts "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
puts "4) setupGPIO: will setup GPIOs for Telo board"
puts "5) showGPIO: will show current GPIO config registers"
puts "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
puts "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
puts "8) showAmbaClk: will show current config registers for Amba Bus Clock"
puts "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
puts "10) showArmClk: will show current config registers for Arm Bus Clock"
puts "11) setupArmClk: will setup Amba Bus Clock=450MHz"
puts "12) ooma_board_detect: will show which version of Telo you have"
puts "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
puts "14) showDDR2: will show DDR2 config registers"
puts "15) showWatchdog: will show current regster config for watchdog"
puts "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
puts "17) bootNOR: will boot Telo from NOR"
puts "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
puts "19) putcUART0: will print a character on UART0"
puts "20) putsUART0: will print a string on UART0"
puts "21) trainDDR2: will run DDR2 training program"
puts "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
}
# mrw,mmw from davinci.cfg
# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
set value ""
ocd_mem2array value 32 $reg 1
return $value(0)
}
# read a 64-bit register (memory mapped)
proc mr64bit {reg} {
set value ""
ocd_mem2array value 32 $reg 2
return $value
}
# write a 64-bit register (memory mapped)
proc mw64bit {reg value} {
set high [expr $value >> 32]
set low [expr $value & 0xffffffff]
#puts [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
mww $reg $low
mww [expr $reg+4] $high
}
# mmw: "memory modify word", updates value of $reg
# $reg <== ((value & ~$clearbits) | $setbits)
proc mmw {reg setbits clearbits} {
set old [mrw $reg]
set new [expr ($old & ~$clearbits) | $setbits]
mww $reg $new
}
proc showNOR {} {
puts "This is the current NOR setup"
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
puts [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
puts [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
puts [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
puts [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
puts [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
puts [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
puts [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
puts [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
puts [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
}
proc showGPIO {} {
puts "This is the current GPIO register setup"
# GPIO outputs register
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# GPIO Output Enable register
set GPIO_OE_REG [regs GPIO_OE_REG]
set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
# GPIO input register
set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set MUX_CONF_REG [regs MUX_CONF_REG]
set SYSCONF_REG [regs SYSCONF_REG]
set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
puts [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
puts [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
puts [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
puts [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
puts [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
puts [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
puts [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
puts [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
puts [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
puts [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
proc showAmbaClk {} {
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
puts [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
puts [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)]
puts [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
puts [format "w: %d" $w]
puts [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
}
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
proc setupAmbaClk {} {
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
set w [config w_amba]
set x [config x_amba]
set y [config y_amba]
puts [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
#puts [format "setupAmbaClk: w= %d" $w]
#puts [format "setupAmbaClk: x= %d" $x]
#puts [format "setupAmbaClk: y= %d" $y]
# set PLL into BYPASS mode using MUX
mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
# do an internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
# openocd smallest resolution is 1ms so, wait 1ms
sleep 1
# disable the PLL
mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
# wait 1ms
sleep 1
# enable the PLL
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
sleep 1
# set X, W and X
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
puts "Wating for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
proc showArmClk {} {
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
puts [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
puts [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)]
puts [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
puts [format "w: %d" $w]
puts [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
}
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
# Arm Clock is used by two ARM1136 cores
proc setupArmClk {} {
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
set w [config w_arm]
set x [config x_arm]
set y [config y_arm]
puts [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
#puts [format "setupArmClk: w= %d" $w]
#puts [format "setupArmaClk: x= %d" $x]
#puts [format "setupArmaClk: y= %d" $y]
# set PLL into BYPASS mode using MUX
mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
# do an internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
# openocd smallest resolution is 1ms so, wait 1ms
sleep 1
# disable the PLL
mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
# wait 1ms
sleep 1
# enable the PLL
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
sleep 1
# set X, W and X
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
puts "Wating for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
}
proc setupPLL {} {
puts "PLLs setup"
setupAmbaClk
setupArmClk
}
# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
proc setupDDR2 {} {
puts "Configuring DDR2"
set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
set MEMORY_CR [regs MEMORY_CR]
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
set DDR_RST [regs DDR_RST]
# put DDR controller in reset (so that it is reset and correctly configured)
# this is only necessary if DDR was previously confiured
# and not reset.
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
set M [expr 1024 * 1024]
set DDR_SZ_1024M [expr 1024 * $M]
set DDR_SZ_256M [expr 256 * $M]
set DDR_SZ_128M [expr 128 * $M]
set DDR_SZ_64M [expr 64 * $M]
# ooma_board_detect returns DDR2 memory size
set tmp [ooma_board_detect]
if {$tmp == "128M"} {
puts "DDR2 size 128MB"
set ddr_size $DDR_SZ_128M
} elseif {$tmp == "256M"} {
puts "DDR2 size 256MB"
set ddr_size $DDR_SZ_256M
} else {
puts "Don't know how to handle this DDR2 size?"
}
# Memory setup register
mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
# disbale ROM remap
mww $MEMORY_CR 0x0
# Take DDR controller out of reset
mmw $BLOCK_RESET_REG $DDR_RST 0x0
# min. 20 ops delay
sleep 1
# This will setup Denali DDR2 controller
if {$tmp == "128M"} {
configureDDR2regs_128M
} elseif {$tmp == "256M"} {
configureDDR2regs_256M
} else {
puts "Don't know how to configure DDR2 setup?"
}
}
proc showDDR2 {} {
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
set tmp [mr64bit $DENALI_CTL_00_DATA]
puts [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_01_DATA]
puts [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_02_DATA]
puts [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_03_DATA]
puts [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_04_DATA]
puts [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_05_DATA]
puts [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_06_DATA]
puts [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_07_DATA]
puts [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_08_DATA]
puts [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_09_DATA]
puts [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_10_DATA]
puts [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_11_DATA]
puts [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_12_DATA]
puts [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_13_DATA]
puts [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_14_DATA]
puts [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_15_DATA]
puts [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_16_DATA]
puts [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_17_DATA]
puts [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_18_DATA]
puts [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_19_DATA]
puts [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_20_DATA]
puts [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
}
proc initC100 {} {
# this follows u-boot/cpu/arm1136/start.S
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
# unlock writing to IOCTRL register
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
# enable address lines A15-A21
mmw $GPIO_IOCTRL_REG 0xf 0x0
# set ARM into supervisor mode (SVC32)
# disable IRQ, FIQ
# Do I need this in JTAG mode?
# it really should be done as 'and ~0x1f | 0xd3 but
# openocd does not support this yet
reg cpsr 0xd3
# /*
# * flush v4 I/D caches
# */
# mov r0, #0
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
arm11 mcr c100.cpu 15 0 7 7 0 0x0
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
arm11 mcr c100.cpu 15 0 8 7 0 0x0
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
arm11 mrc c100.cpu 15 0 1 0 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
# orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
arm11 mcr c100.cpu 15 0 1 0 0 0x401002
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
# APB init
# // Setting APB Bus Wait states to 1, set post write
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
mww [expr $APB_ACCESS_WS_REG] 0x40
# AHB init
# // enable all 6 masters for ARAM
mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
# // enable all 6 masters for EBUS
mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
# ARAM init
# // disable pipeline mode in ARAM
# I don't think this is documented anywhere?
mww $INTC_ARM1_CONTROL_REG 0x1
# configure clocks
setupPLL
# enable cache
# ? (u-boot does nothing here)
# need to enable UART0 to show boot progress on serial console
setupUART0
# DDR2 memory init
setupDDR2
putsUART0 "C100 initialization complete.\n"
puts "C100 initialization complete."
}
# show current state of watchdog timer
proc showWatchdog {} {
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
puts [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
puts [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
}
# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
# this will trigger watchdog reset
# the sw. reset does not work on C100
# watchdog reset effectively works as hw. reset
proc reboot {} {
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
# allow the counter to count to high value before triggering
# this is because regsiter writes are slow over JTAG and
# I don't want to miss the high_bound==curr_count condition
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
puts "JTAG speed lowered to 100kHz"
jtag_khz 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
puts -nonewline "Wating for watchdog to trigger..."
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
# puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
# sleep 1
#
#}
while {[c100.cpu curstate] != "running"} { sleep 1}
puts "done."
puts [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
}
source [find c100.cfg]
# basic register defintion for C100
source [find c100regs.tcl]
# board-config info
source [find c100config.tcl]
# C100 helper functions
source [find c100helper.tcl]
# Telo board & C100 support trst and srst
# Note that libftd2xx.so tries to assert srst
# which break this script
# use libftdi.so library instead with this script
# make the reset asserted to
# allow RC circuit to discharge for: [ms]
jtag_nsrst_assert_width 100
jtag_ntrst_assert_width 100
# don't talk to JTAG after reset for: [ms]
jtag_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
jtag_khz 100
# this will setup Telo board
setupTelo
#turn up the JTAG speed
jtag_khz 3000
puts "JTAG speek now 3MHz"
puts "type helpC100 to get help on C100"
}
$_TARGETNAME configure -event reset-deassert-post {
# Force target into ARM state.
# soft_reset_halt # not implemented on ARM11
puts "Detected SRSRT asserted on C100.CPU"
}
$_TARGETNAME configure -event reset-assert-post {
puts "Assering reset"
#sleep 10
}
proc power_restore {} { puts "Sensed power restore. No action." }
proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
# it's really 16MB but the upper 8mb is controller via gpio
# openocd does not support 'complex reads/writes' to NOR
flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
# writing data to memory does not work without this
memwrite burst disable_______________________________________________
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