On Tue, Sep 29, 2009 at 11:14 PM, David Brownell <davi...@pacbell.net> wrote:
> What hardware? Board is vsc7501(vitesse) which used ARM926ejs core. > I've seen such issues with the OMAP5912, which has > what seems to be an early ARM926 core. The most > strange thing is that the EmbeddedICE unit seems to > misbehave ... as in, the "debug_status" register > likes to read as zero after it halts. Meanwhile > the "debug_ctrl" register seems to indicate that > it has inded halted. Yet ... CPSR is garbaged, > reporting that it's in ARM state (not so!) and > that the core mode (svc/fiq/user/abort/etc) is > some unknown value. I cannot halt it but after type `regs' command it shows me almost registers are 0x00000000. "debug_ctrl" is not zero(no log now). Others I'm not sure. > > That is, *sometimes* it gets into those wierd > modes. A few other times it's behaved normally. Yes, I can remember that 3 months ago I got same matter. But it disappeared quickly(retry one more time) so we didnt notice that is a problem. Unfortunately, it's in the abnormal mode several days. Regards -- zeal _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
