Hello David, Saturday, September 26, 2009, 8:11:26 AM, you wrote:
DB> REQUEST: someone with the IEEE JTAG spec, please verify that DB> entry to IR_Capture state is required to load the shift register DB> with xxxxx01 bits (as I'm told it does). Not the actual spec, but the Boundary-Scan Handbook says this: CAPTURE-IR In this controller state, the shift-register[16] contained in the Instruction Register parallel loads a pattern of fixed logic values on the rising edge of TCK. The two least significant bits[17] are assigned the values "01". Any higher-order bits of the Instruction Register, if they exist, may receive fixed bit values or design specific values. This bit pattern is not necessarily an instruction; it has significance as a test pattern for the integrity of the 1149.1 circuitry as will be seen in Chapters 3 and 5. When the TAP Controller is in CAPTURE-IR, the controller enters either the EXIT1-IR state if TMS is high or the SHIFT-IR state if TMS is low. [16] Registers are constructed with dual ranks, a shiftable part and a hold part to prevent rippling, due to shifting, from being visible to downstream logic. When we say a register is selected or shifted, we mean the shift portion of it which is connected between TDI and TDO. [17] Throughout this book, any pattern of bits will be displayed with the most significant bit on the left, through to the least significant on the right. The least significant bit would be the first bit shifted into TDI or out from TDO. -- WBR, Igor mailto:skochin...@mail.ru _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
