simon qian a écrit : > As I know, for STM32, JTAG speed should be below 500KHz. I tried all the way down to 1khz with no success. How do you explain that it works nicely with the evaluation board with the same device? It works also correctly with the J-Link in both cases.
One weird thing I saw was that the jtag_nsrst_delay value is a don't care. I can put 100, 1000 or 10000 and it is about the same. In the specs it says that it is the time that the nsrst is asserted but in reality it seems to be the time between retries. I say that because if I change it to 10000 it increases the time between the error lines. The reset of the processor is about the same. I disabled the watchdog for that test so I know that it is not the watchdog that reset the board. The problem is at the software for the Olimex Tiny device. There are pullups on the lines as required. When trying to run the leds on my board are flashing on and off like creasy. They cannot turn on without the code running as they are on shift registers. This means that it can reset the device but cannot halt it. With 200khz I get a bit different result. I do have to run it several times to get it to pass the first part though. Most of the time the result is similar to that of other speed. [mic...@localhost STM32-SK_LCD_Demo]$ openocd -f stm32_OlimexTiny.cfg Open On-Chip Debugger 0.3.0-in-development (2009-09-12-17:22) svn:2700M $URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $ For bug reports, read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS 200 kHz jtag_nsrst_delay: 100 jtag_ntrst_delay: 100 Warn : use 'stm32.cpu' as target identifier, not '0' Info : device: 4 "2232C" Info : deviceID: 364511236 Info : SerialNumber: FTPX9QML A Info : Description: Olimex OpenOCD JTAG TINY A Info : clock speed 200 kHz Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3) Info : JTAG tap: stm32.bs tap/device found: 0xcb210041 (mfg: 0x020, part: 0xb210, ver: 0xc) Error: JTAG tap: stm32.bs got: 0xcb210041 (mfg: 0x020, part: 0xb210, ver: 0xc) Error: JTAG tap: stm32.bs expected 1 of 5: 0x06412041 (mfg: 0x020, part: 0x6412, ver: 0x0) Error: JTAG tap: stm32.bs expected 2 of 5: 0x06410041 (mfg: 0x020, part: 0x6410, ver: 0x0) Error: JTAG tap: stm32.bs expected 3 of 5: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1) Error: JTAG tap: stm32.bs expected 4 of 5: 0x06414041 (mfg: 0x020, part: 0x6414, ver: 0x0) Error: JTAG tap: stm32.bs expected 5 of 5: 0x06418041 (mfg: 0x020, part: 0x6418, ver: 0x0) Error: trying to validate configured JTAG chain anyway... Error: AHBAP Cached values: dp_select 0x0, ap_csw 0xa2000012, ap_tar 0xffffffff Error: SWJ-DP STICKY ERROR Error: Read MEM_AP_CSW 0x11800042, MEM_AP_TAR 0x11800042 Warn : Invalid ACK in SWJDP transaction Warn : Invalid ACK in SWJDP transaction Michel -- Tired of Microsoft's rebootive multitasking? then it's time to upgrade to Linux. http://home.comcast.net/~mcatudal _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
