Holger Freyther wrote: > On Friday 28 August 2009 19:28:50 Magnus Lundin wrote: > > >> The usual way for OpenOCD targets to check if a PROCESSOR_HALTED flag >> has been set is not to do it in the halt command but rather in the poll >> command. >> This in general improves performance when using long roundtrip >> interfaces like USB. >> > > Okay, I was not sure about the state transitions and such, I can remove that > part and plant some asserts in the other paths to make sure they are not > called before the core is paused. > > >> This does not affect stability but only moves the actual run state >> detection, and affect the halt and resume commands. >> >> Some other checks lite testing for DTRRXfull and wait for previous >> instruction patch definetly improves stability but they are performance >> killer especially for debug work like single stepping. >> > > I sincerely disagree here. These bits directly come out of the Cortex A8 > Technical Reference Manual and not following them is not making things fast > but it makes them unreliable. > > In other words, why would ever want to read half of the result? > To speed up debugging !! I did read the Cortex_A8 TRM when I first started to work on that code :), and I also tested if things were reasonably stable without the checks.
In many situations it is not necessary to check those flag bits and instead rely on bus/instruction timing. The core is inhalted debug and only exectuing opcodes that we have pushed to it for single instruction execution. So we can make educated guesses about the time it takes before the results will be available or the preceding instruction finishes ecxecution. This timing is related to the swjdp->memaccess_tck field that was added to all cortex targets. So it is not unresonable to let crazy people make their own choise to trust fate and speed up dubgging by not always checking theese flags. Thus different debug modes SAFE/FAST , but I do agree there should a safe mode and the original code did not have that. >> Perhaps we need a debugmode=FAST / debugmode = STABLE flag to control >> speed vs stability. >> >> When developing the cortex_a8 code I had the "enable ITR for code >> execution" in the init script. In general we try put put this kind of >> target initialisations in TCL setup/reset scripts. >> > > Ah great, from my understanding the code running on the core can access the > L3 > and L4 registers as well. So in theory and practice the code running on the > core has changed the ITR flag. This is why I put it into the debug_entry > right > after saving the old DSCR to make sure it is enabled. > > > maybe this clear things up, I will need to single step through linux to see > when stuff breaks in OpenOCD... my assumption is enabling the MMU but I will > find this out next week. > > z, > > The really important thing now is that there are several people working on and testing these things. I am not saying I am right but I do have some experince whith this code and I hope my comments can help in directing further work. Thank you for Your (several of you :) ) work with this code. Best regards Magnus _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
