Let's try to organize this a little and summarize the status:
1. Last time I tried was *r2604*:
https://lists.berlios.de/pipermail/openocd-development/2009-August/010035.html
To reproduce this, you have to apply the four patches in attachment of
that mail to r2604.
Fred and Matt: Please try to exactly reproduce this and in case of
differences or other issues, send detailed report.
Matt: As you can see in above mail, halt and resume seem to work there.
2. When we agree on status of (1), then it's time to test recent
trunk. As Øyvind mentioned in
https://lists.berlios.de/pipermail/openocd-development/2009-August/010073.html
he applied 3 of 4 patches from (1) (thanks!). To test this, we have to
apply remaining patch (attachment) and test if result is the same like
in (1). I did so and got the same result as in (1) with *r2619* and
single patch in attachment.
Fred and Matt: Please try to exactly reproduce this and in case of
differences or other issues, send detailed report.
3. When we agree on (1) and (2), the further steps could be:
a) Review/fix/rewrite remaining patch to get it applied. Dave's recent
version of this patch is in
https://lists.berlios.de/pipermail/openocd-development/2009-August/010041.html
btw (see attachment, too).
b) Fix the issues mentioned in (1):
- Fix "OLD SYNTAX: DEPRECATED - use jtag_khz, not jtag_speed"
- Fix "invalid mode value encountered" warnings
- Fix "soft_reset_halt" segfault
- Update eLinux OpenOCD Beagle page
- ...
Best regards
Dirk
Matt Hsu wrote:
Øyvind Harboe wrote:
Did you try with the patches I committed today?
Hi Øyvind,
Thanks for your reply.
Yes. I applied the patch your committed. It definitely works.
The jtag session could be established.
The problem is I would like to issue commands such as reset halt,
bp, resume.
The source code shown their implementation are NULL.
So I'm curious why coretex_a8 does not have these support?
Or why Magnus's patches were not merged?
Cheers,
Matt
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---
src/jtag/core.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -469,6 +469,14 @@ void jtag_add_tlr(void)
{
jtag_prelude(TAP_RESET);
jtag_set_error(interface_jtag_add_tlr());
+
+ /*
+ * Add a bunch of clocks after TLR entry to force SWD reset (newer
+ * ARM cores; just in case, ~50 cycles), switch on ICEpick power
+ * domains (for some TI parts, ~100 cycles), etc
+ */
+ jtag_set_error(interface_jtag_add_runtest(100, TAP_RESET));
+
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
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