On 8/6/09 2:14 PM, "Ferdinand Postema" <ferdin...@postema.eu> wrote:
> I found a solution to my problem. It seems that this module needs one
> clock cycle in state RUN TEST/IDLE between the setting of the vector
> catch and the reset. Then it works perfectly. I tested it with the
> RTCK-feature and on 1 kHz, 2 kHz and 4 kHz. It didn't work at 8kHz,
> because the chip clock falls back to 32 kHz at reset. I have attached a
> patch file to include the extra cycle in state RUN TEST/IDLE.
>
> Ferdinand Postema schreef:
> Index: src/target/arm7_9_common.c
> ===================================================================
> --- src/target/arm7_9_common.c (revision 2571)
> +++ src/target/arm7_9_common.c (working copy)
> @@ -1015,6 +1015,7 @@
> {
/* program vector catch register to catch reset vector */
> embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH],
> 0x1);
+ jtag_add_runtest(1, jtag_get_end_state());
}
else
{
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After being on vacation for several weeks, I started looking at this same
problem today except that I am working with a AT91SAM9G20 using a jlink
dongle. I tried your patch and it fixes my problem as well.
How did you discover this fix?
I am now curious whether this change will have any affect on non-Atmel
processors. If it doesn't, I think this needs to be committed.
Gary
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