On 7/14/09 7:55 AM, "Alan Carvalho de Assis" <acas...@gmail.com> wrote:
> Hi Gary,
>
> On 7/13/09, Gary Carlson <gcarl...@carlson-minot.com> wrote:
>>
>> I think your board is being held in reset by something other then the J-link
>> dongle. If the board is in reset and the jlink device can't free it, your
>> will get the problem you described. You can prove that by taking your
>> working board and holding the reset button down while you start the openocd.
>> It will break 100% of the time too.
>>
>> Have you looked at your board reset signals on a scope?
>>
>
> I think there is not issue with reset signal because the board can to
> start its bootloader correctly when there is not JTAG attached. Anyway
> I will investigate the reset signals.
>
> Thank you very much,
>
> Regards,
>
> Alan
That may be a possibility. The JTAG dongle itself may not be clearing the
reset signal. If definitely is worth confirming the state of the reset
signals by inspection because I still suspect that may be factoring into
your problems.
I am not familiar with your board and what I am going to mention may not
apply. One of the other things that can trip up people using debuggers is
watch-dog timers. Does this board have any external devices (i.e. FPGA or
dedicated WDT) that can activate the reset signal(s) to the CPU? Those can
cause a great deal of grief also.
In any case I am pretty sure that your specific problem is different then
recent patches were put in place to address.
Gary
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