I attach a patch which makes lpc2478.cfg file more "standard" and - what
is most important - correct (it's working [; ). I've also added some
comments which try to clarify the meaning of all that's in there.
4\/3!!
Index: tcl/target/lpc2478.cfg
===================================================================
--- tcl/target/lpc2478.cfg (revision 2268)
+++ tcl/target/lpc2478.cfg (working copy)
@@ -1,35 +1,49 @@
-# Testing feeedback wanted!
-set _CHIPNAME lpc2478
-set _ENDIAN little
-set _CPUTAPID 0x4f1f0f0f
+# NXP LPC2478 ARM7TDMI-S with 512kB Flash and 64kB Local On-Chip SRAM (98kB
total), clocked with 4MHz internal RC oscillator
-# Use RCLK. If RCLK is not available fall back to 500kHz.
-#
-# Depending on cabling you might be able to eek this up to 2000kHz.
-jtag_rclk 500
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2478
+}
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
-#use combined on interfaces or targets that can't set TRST/SRST separately
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x4f1f0f0f
+}
+
+#delays on reset lines
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+# LPC2000 -> SRST causes TRST
reset_config trst_and_srst srst_pulls_trst
-
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi-s_r4
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000
-work-area-size 0x4000 -work-area-backup 0
+# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip
SRAM)
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000
-work-area-size 0x10000 -work-area-backup 0
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
soft_reset_halt
- # FIX!!!! should we remap the range below??? Is this applicable to
- # Copied from LPC2148.
- #do not remap 0x0000-0x0020 to anything but the flash
+ # Do not remap 0x0000-0x0020 to anything but the Flash
mwb 0xE01FC040 0x01
}
+# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
+# After reset the chip uses its internal 4MHz RC oscillator.
+# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc
checksum]
+flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum
-flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum
+# Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 =
666kHz, so use 500.
+jtag_rclk 500
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