zengjie wrote: > My board used vitesse chip and the core is ARM926ejs. From the pin > table, there are 8 bit for data bus and 24 bit for address bus. > > Q: what kind of flash, mode (8/16 bit)? > > FLASH is EN29LV640T/B, 64 Megabit (8M x 8-bit / 4M x 16-bit) Flash > Memory Boot Sector Flash Memory. > The mode is 8-bit I think since it connected DQ0~DQ7 as data channel. You are using an 16-bit flash in 8-bit mode, making it effectively an 8-bit flash with shifted address lines. In that case, you need the x16_as_x8 option, which explains why your probe fails.
> > Q: bus width of the CPU? > > You mean address bus width? If so, it's configurable and the value is > 8 or 16 bit. All of the addr pin(24) connect with flash. > > I set this bus width to 16 bit through change a register. This can not work if the flash is connected with only 8 data lines. If only DQ0-DQ7 is connected, you need to configure the CPU bus to be 8 bits wide when accessing the flash. > Now start to talk the openocd config. > > #### flash bank #### > # chip_width(addr width) is 16 bit, bus_width(data width) is 8 bit > flash bank cfi 0x10000000 0x8000000 2 1 0 > > Is it correct? In fact, I am not very sure the meaning of chip_width > and bus_width in bank structure from source code. chip_width is 1, since 1 byte (8 bits) are connected, and bus_width should be 1, too. Furthermore, you need the x16_as_x8 option to tell openocd that the flash uses shifted address lines. I hope the address lines are connected correctly (with A-1 on the flash connected to A0 on the CPU)? cu Michael _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
