Whitespace fixes.
---
src/target/cortex_m3.c | 358 +++++++++++++++++++++---------------------
src/target/target_request.c | 48 ++---
2 files changed, 203 insertions(+), 203 deletions(-)
Whitespace fixes.
---
src/target/cortex_m3.c | 358 +++++++++++++++++++++---------------------
src/target/target_request.c | 48 ++---
2 files changed, 203 insertions(+), 203 deletions(-)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -64,7 +64,7 @@ target_type_t cortexm3_target =
.arch_state = armv7m_arch_state,
.target_request_data = cortex_m3_target_request_data,
-
+
.halt = cortex_m3_halt,
.resume = cortex_m3_resume,
.step = cortex_m3_step,
@@ -72,7 +72,7 @@ target_type_t cortexm3_target =
.assert_reset = cortex_m3_assert_reset,
.deassert_reset = cortex_m3_deassert_reset,
.soft_reset_halt = cortex_m3_soft_reset_halt,
-
+
.get_gdb_reg_list = armv7m_get_gdb_reg_list,
.read_memory = cortex_m3_read_memory,
@@ -80,9 +80,9 @@ target_type_t cortexm3_target =
.bulk_write_memory = cortex_m3_bulk_write_memory,
.checksum_memory = armv7m_checksum_memory,
.blank_check_memory = armv7m_blank_check_memory,
-
+
.run_algorithm = armv7m_run_algorithm,
-
+
.add_breakpoint = cortex_m3_add_breakpoint,
.remove_breakpoint = cortex_m3_remove_breakpoint,
.add_watchpoint = cortex_m3_add_watchpoint,
@@ -152,12 +152,12 @@ int cortex_m3_write_debug_halt_mask(targ
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
-
+
return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
@@ -167,10 +167,10 @@ int cortex_m3_clear_halt(target_t *targe
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
-
+
/* Read Debug Fault Status Register */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
@@ -187,20 +187,20 @@ int cortex_m3_single_step_core(target_t
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dhcsr_save;
-
+
/* backup dhcsr reg */
dhcsr_save = cortex_m3->dcb_dhcsr;
-
+
/* mask interrupts if not done already */
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
LOG_DEBUG(" ");
-
+
/* restore dhcsr reg */
- cortex_m3->dcb_dhcsr = dhcsr_save;
+ cortex_m3->dcb_dhcsr = dhcsr_save;
cortex_m3_clear_halt(target);
-
+
return ERROR_OK;
}
@@ -211,14 +211,14 @@ int cortex_m3_exec_opcode(target_t *targ
swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 savedram;
int retvalue;
-
+
mem_ap_read_u32(swjdp, 0x20000000, &savedram);
mem_ap_write_u32(swjdp, 0x20000000, opcode);
cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15);
cortex_m3_single_step_core(target);
armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram);
-
+
return retvalue;
}
@@ -240,28 +240,28 @@ int cortex_m3_endreset_event(target_t *t
{
int i;
u32 dcb_demcr;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
- cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
+ cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
-
+
/* this regsiter is used for emulated dcc channel */
mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
-
+
/* Enable debug requests */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
-
+
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
-
+
/* Enable trace and dwt */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
/* Monitor bus faults */
@@ -276,7 +276,7 @@ int cortex_m3_endreset_event(target_t *t
{
target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
}
-
+
/* Restore DWT registers */
for (i = 0; i < cortex_m3->dwt_num_comp; i++)
{
@@ -285,12 +285,12 @@ int cortex_m3_endreset_event(target_t *t
target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function);
}
swjdp_transaction_endcheck(swjdp);
-
+
armv7m_invalidate_core_regs(target);
-
+
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
-
+
return ERROR_OK;
}
@@ -302,7 +302,7 @@ int cortex_m3_examine_debug_reason(targe
/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
/* only check the debug reason if we don't know it already */
-
+
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
@@ -343,11 +343,11 @@ int cortex_m3_examine_exception_reason(t
break;
case 4: /* Memory Management */
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
break;
case 5: /* Bus Fault */
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
break;
case 6: /* Usage Fault */
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
@@ -435,15 +435,15 @@ int cortex_m3_debug_entry(target_t *targ
armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
armv7m->exception_number = 0;
}
-
+
if (armv7m->exception_number)
{
cortex_m3_examine_exception_reason(target);
}
- LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s",
+ LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
- *(u32*)(armv7m->core_cache->reg_list[15].value),
+ *(u32*)(armv7m->core_cache->reg_list[15].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
if (armv7m->post_debug_entry)
@@ -456,7 +456,7 @@ int cortex_m3_poll(target_t *target)
{
int retval;
enum target_state prev_target_state = target->state;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
@@ -469,19 +469,19 @@ int cortex_m3_poll(target_t *target)
target->state = TARGET_UNKNOWN;
return retval;
}
-
+
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
/* check if still in reset */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
-
+
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
target->state = TARGET_RESET;
return ERROR_OK;
}
}
-
+
if (target->state == TARGET_RESET)
{
/* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
@@ -490,7 +490,7 @@ int cortex_m3_poll(target_t *target)
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
}
-
+
if (cortex_m3->dcb_dhcsr & S_HALT)
{
target->state = TARGET_HALTED;
@@ -499,7 +499,7 @@ int cortex_m3_poll(target_t *target)
{
if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
return retval;
-
+
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
if (prev_target_state == TARGET_DEBUG_RUNNING)
@@ -511,7 +511,7 @@ int cortex_m3_poll(target_t *target)
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
}
-
+
/*
if (cortex_m3->dcb_dhcsr & S_SLEEP)
target->state = TARGET_SLEEP;
@@ -522,27 +522,27 @@ int cortex_m3_poll(target_t *target)
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
#endif
-
+
return ERROR_OK;
}
int cortex_m3_halt(target_t *target)
{
- LOG_DEBUG("target->state: %s",
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
-
+
if (target->state == TARGET_HALTED)
{
LOG_DEBUG("target was already halted");
return ERROR_OK;
}
-
+
if (target->state == TARGET_UNKNOWN)
{
LOG_WARNING("target was in unknown state when halt was requested");
}
-
- if (target->state == TARGET_RESET)
+
+ if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
@@ -555,8 +555,8 @@ int cortex_m3_halt(target_t *target)
* debug entry was already prepared in cortex_m3_prepare_reset_halt()
*/
target->debug_reason = DBG_REASON_DBGRQ;
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
}
@@ -564,7 +564,7 @@ int cortex_m3_halt(target_t *target)
cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
target->debug_reason = DBG_REASON_DBGRQ;
-
+
return ERROR_OK;
}
@@ -579,8 +579,8 @@ int cortex_m3_soft_reset_halt(struct tar
/* Enter debug state on reset, cf. end_reset_event() */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
-
- /* Request a reset */
+
+ /* Request a reset */
mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
target->state = TARGET_RESET;
@@ -605,7 +605,7 @@ int cortex_m3_soft_reset_halt(struct tar
timeout++;
alive_sleep(1);
}
-
+
return ERROR_OK;
}
@@ -615,49 +615,49 @@ int cortex_m3_resume(struct target_s *ta
armv7m_common_t *armv7m = target->arch_info;
breakpoint_t *breakpoint = NULL;
u32 resume_pc;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (!debug_execution)
{
target_free_all_working_areas(target);
cortex_m3_enable_breakpoints(target);
cortex_m3_enable_watchpoints(target);
}
-
+
if (debug_execution)
{
/* Disable interrupts */
/* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
- * This is probably the same issue as Cortex-M3 Errata 377493:
+ * This is probably the same issue as Cortex-M3 Errata 377493:
* C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
/* Make sure we are in Thumb mode */
- buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
+ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
- if (!current)
+ if (!current)
{
buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
armv7m->core_cache->reg_list[15].dirty = 1;
armv7m->core_cache->reg_list[15].valid = 1;
}
-
+
resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
armv7m_restore_context(target);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
@@ -670,10 +670,10 @@ int cortex_m3_resume(struct target_s *ta
cortex_m3_set_breakpoint(target, breakpoint);
}
}
-
+
/* Restart core */
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
-
+
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
@@ -690,7 +690,7 @@ int cortex_m3_resume(struct target_s *ta
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
}
-
+
return ERROR_OK;
}
@@ -712,25 +712,25 @@ int cortex_m3_step(struct target_s *targ
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32))))
cortex_m3_unset_breakpoint(target, breakpoint);
-
+
target->debug_reason = DBG_REASON_SINGLESTEP;
-
+
armv7m_restore_context(target);
-
+
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-
+
/* set step and clear halt */
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
-
+
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
@@ -749,23 +749,23 @@ int cortex_m3_assert_reset(target_t *tar
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int assert_srst = 1;
-
- LOG_DEBUG("target->state: %s",
+
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
-
+
if (!(jtag_reset_config & RESET_HAS_SRST))
{
LOG_ERROR("Can't assert SRST");
return ERROR_FAIL;
}
-
+
/* Enable debug requests */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
-
+
mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
-
+
if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
@@ -774,11 +774,11 @@ int cortex_m3_assert_reset(target_t *tar
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
-
+
/* clear C_HALT in dhcsr reg */
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
-
- /* Enter debug state on reset, cf. end_reset_event() */
+
+ /* Enter debug state on reset, cf. end_reset_event() */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
}
else
@@ -786,18 +786,18 @@ int cortex_m3_assert_reset(target_t *tar
/* Enter debug state on reset, cf. end_reset_event() */
mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
}
-
+
/* following hack is to handle luminary reset
* when srst is asserted the luminary device seesm to also clear the debug registers
* which does not match the armv7 debug TRM */
-
+
if (strcmp(target->variant, "lm3s") == 0)
{
/* get revision of lm3s target, only early silicon has this issue
* Fury Rev B, DustDevil Rev B, Tempest all ok */
-
+
u32 did0;
-
+
if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
{
switch ((did0 >> 16) & 0xff)
@@ -806,7 +806,7 @@ int cortex_m3_assert_reset(target_t *tar
/* all Sandstorm suffer issue */
assert_srst = 0;
break;
-
+
case 1:
case 3:
/* only Fury/DustDevil rev A suffer reset problems */
@@ -816,7 +816,7 @@ int cortex_m3_assert_reset(target_t *tar
}
}
}
-
+
if (assert_srst)
{
/* default to asserting srst */
@@ -842,10 +842,10 @@ int cortex_m3_assert_reset(target_t *tar
mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
}
}
-
+
target->state = TARGET_RESET;
jtag_add_sleep(50000);
-
+
armv7m_invalidate_core_regs(target);
if (target->reset_halt)
@@ -854,25 +854,25 @@ int cortex_m3_assert_reset(target_t *tar
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
-
+
return ERROR_OK;
}
int cortex_m3_deassert_reset(target_t *target)
-{
- LOG_DEBUG("target->state: %s",
+{
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
-
+
/* deassert reset lines */
jtag_add_reset(0, 0);
-
+
return ERROR_OK;
}
void cortex_m3_enable_breakpoints(struct target_s *target)
{
breakpoint_t *breakpoint = target->breakpoints;
-
+
/* set any pending breakpoints */
while (breakpoint)
{
@@ -887,11 +887,11 @@ int cortex_m3_set_breakpoint(struct targ
int retval;
int fp_num=0;
u32 hilo;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
if (breakpoint->set)
@@ -899,7 +899,7 @@ int cortex_m3_set_breakpoint(struct targ
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
-
+
if (cortex_m3->auto_bp_type)
{
breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
@@ -958,7 +958,7 @@ int cortex_m3_unset_breakpoint(struct ta
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
-
+
if (breakpoint->type == BKPT_HARD)
{
int fp_num = breakpoint->set - 1;
@@ -1006,7 +1006,7 @@ int cortex_m3_add_breakpoint(struct targ
#ifdef ARMV7_GDB_HACKS
if (breakpoint->length != 2) {
/* XXX Hack: Replace all breakpoints with length != 2 with
- * a hardware breakpoint. */
+ * a hardware breakpoint. */
breakpoint->type = BKPT_HARD;
breakpoint->length = 2;
}
@@ -1036,11 +1036,11 @@ int cortex_m3_add_breakpoint(struct targ
LOG_INFO("only breakpoints of two bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available--;
cortex_m3_set_breakpoint(target, breakpoint);
-
+
return ERROR_OK;
}
@@ -1049,13 +1049,13 @@ int cortex_m3_remove_breakpoint(struct t
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (cortex_m3->auto_bp_type)
{
breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
@@ -1065,10 +1065,10 @@ int cortex_m3_remove_breakpoint(struct t
{
cortex_m3_unset_breakpoint(target, breakpoint);
}
-
+
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available++;
-
+
return ERROR_OK;
}
@@ -1076,7 +1076,7 @@ int cortex_m3_set_watchpoint(struct targ
{
int dwt_num=0;
u32 mask, temp;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
@@ -1132,7 +1132,7 @@ int cortex_m3_unset_watchpoint(struct ta
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list;
int dwt_num;
-
+
if (!watchpoint->set)
{
LOG_WARNING("watchpoint not set");
@@ -1160,7 +1160,7 @@ int cortex_m3_add_watchpoint(struct targ
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
@@ -1171,14 +1171,14 @@ int cortex_m3_add_watchpoint(struct targ
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
cortex_m3->dwt_comp_available--;
-
+
return ERROR_OK;
}
@@ -1187,27 +1187,27 @@ int cortex_m3_remove_watchpoint(struct t
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (watchpoint->set)
{
cortex_m3_unset_watchpoint(target, watchpoint);
}
-
+
cortex_m3->dwt_comp_available++;
-
+
return ERROR_OK;
}
void cortex_m3_enable_watchpoints(struct target_s *target)
{
watchpoint_t *watchpoint = target->watchpoints;
-
+
/* set any pending watchpoints */
while (watchpoint)
{
@@ -1223,12 +1223,12 @@ int cortex_m3_load_core_reg_u32(struct t
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
/* read a normal core register */
retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
-
+
if (retval != ERROR_OK)
{
LOG_ERROR("JTAG failure %i",retval);
@@ -1240,33 +1240,33 @@ int cortex_m3_load_core_reg_u32(struct t
{
/* read other registers */
cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
-
+
switch (num)
{
case 19:
*value = buf_get_u32((u8*)value, 0, 8);
break;
-
+
case 20:
*value = buf_get_u32((u8*)value, 8, 8);
break;
-
+
case 21:
*value = buf_get_u32((u8*)value, 16, 8);
break;
-
+
case 22:
*value = buf_get_u32((u8*)value, 24, 8);
break;
}
-
+
LOG_DEBUG("load from special reg %i value 0x%x", num, *value);
}
else
{
return ERROR_INVALID_ARGUMENTS;
}
-
+
return ERROR_OK;
}
@@ -1274,7 +1274,7 @@ int cortex_m3_store_core_reg_u32(struct
{
int retval;
u32 reg;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
@@ -1285,11 +1285,11 @@ int cortex_m3_store_core_reg_u32(struct
* hack to deal with the fact that gdb will sometimes "forge"
* return addresses, and doesn't set the LSB correctly (i.e., when
* printing expressions containing function calls, it sets LR=0.) */
-
+
if (num == 14)
value |= 0x01;
#endif
-
+
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
@@ -1304,38 +1304,38 @@ int cortex_m3_store_core_reg_u32(struct
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
{
/* write other registers */
-
+
cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
-
+
switch (num)
{
case 19:
buf_set_u32((u8*)®, 0, 8, value);
break;
-
+
case 20:
buf_set_u32((u8*)®, 8, 8, value);
break;
-
+
case 21:
buf_set_u32((u8*)®, 16, 8, value);
break;
-
+
case 22:
buf_set_u32((u8*)®, 24, 8, value);
break;
}
-
+
cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
-
+
LOG_DEBUG("write special reg %i value 0x%x ", num, value);
}
else
{
return ERROR_INVALID_ARGUMENTS;
}
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
@@ -1344,13 +1344,13 @@ int cortex_m3_read_memory(struct target_
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
-
+
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
-
+
/* cortex_m3 handles unaligned memory access */
-
+
switch (size)
{
case 4:
@@ -1366,7 +1366,7 @@ int cortex_m3_read_memory(struct target_
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
}
-
+
return retval;
}
@@ -1376,11 +1376,11 @@ int cortex_m3_write_memory(struct target
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
-
+
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
-
+
switch (size)
{
case 4:
@@ -1390,13 +1390,13 @@ int cortex_m3_write_memory(struct target
retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
+ retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
}
-
+
return retval;
}
@@ -1421,27 +1421,27 @@ int cortex_m3_examine(struct target_s *t
int retval;
u32 cpuid, fpcr, dwtcr, ictr;
int i;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
-
+
if (!target_was_examined(target))
{
target_set_examined(target);
-
+
/* Read from Device Identification Registers */
if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK)
return retval;
-
+
if (((cpuid >> 4) & 0xc3f) == 0xc23)
LOG_DEBUG("CORTEX-M3 processor detected");
LOG_DEBUG("cpuid: 0x%8.8x", cpuid);
-
+
target_read_u32(target, NVIC_ICTR, &ictr);
cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4);
@@ -1450,7 +1450,7 @@ int cortex_m3_examine(struct target_s *t
target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]);
}
-
+
/* Setup FPB */
target_read_u32(target, FP_CTRL, &fpcr);
cortex_m3->auto_bp_type = 1;
@@ -1465,7 +1465,7 @@ int cortex_m3_examine(struct target_s *t
cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
}
LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
-
+
/* Setup DWT */
target_read_u32(target, DWT_CTRL, &dwtcr);
cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF;
@@ -1476,26 +1476,26 @@ int cortex_m3_examine(struct target_s *t
cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i;
}
}
-
+
return ERROR_OK;
}
int cortex_m3_quit(void)
{
-
+
return ERROR_OK;
}
int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
{
u16 dcrdr;
-
+
mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (u8)dcrdr;
*value = (u8)(dcrdr >> 8);
-
+
LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
-
+
/* write ack back to software dcc register
* signify we have read data */
if (dcrdr & (1 << 0))
@@ -1503,7 +1503,7 @@ int cortex_m3_dcc_read(swjdp_common_t *s
dcrdr = 0;
mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
}
-
+
return ERROR_OK;
}
@@ -1514,13 +1514,13 @@ int cortex_m3_target_request_data(target
u8 data;
u8 ctrl;
u32 i;
-
+
for (i = 0; i < (size * 4); i++)
{
cortex_m3_dcc_read(swjdp, &data, &ctrl);
buffer[i] = data;
}
-
+
return ERROR_OK;
}
@@ -1531,22 +1531,22 @@ int cortex_m3_handle_target_request(void
return ERROR_OK;
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
-
+
if (!target->dbg_msg_enabled)
return ERROR_OK;
-
+
if (target->state == TARGET_RUNNING)
{
u8 data;
u8 ctrl;
-
+
cortex_m3_dcc_read(swjdp, &data, &ctrl);
-
+
/* check if we have data */
if (ctrl & (1 << 0))
{
u32 request;
-
+
/* we assume target is quick enough */
request = data;
cortex_m3_dcc_read(swjdp, &data, &ctrl);
@@ -1558,7 +1558,7 @@ int cortex_m3_handle_target_request(void
target_request(target, request);
}
}
-
+
return ERROR_OK;
}
@@ -1570,14 +1570,14 @@ int cortex_m3_init_arch_info(target_t *t
/* prepare JTAG information for the new target */
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
-
+
armv7m->swjdp_info.dp_select_value = -1;
armv7m->swjdp_info.ap_csw_value = -1;
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
/* initialize arch-specific breakpoint handling */
-
+
cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
cortex_m3->arch_info = NULL;
@@ -1586,26 +1586,26 @@ int cortex_m3_init_arch_info(target_t *t
armv7m->pre_debug_entry = NULL;
armv7m->post_debug_entry = NULL;
-
+
armv7m->pre_restore_context = NULL;
armv7m->post_restore_context = NULL;
-
- armv7m_init_arch_info(target, armv7m);
+
+ armv7m_init_arch_info(target, armv7m);
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
-
+
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
-
+
return ERROR_OK;
}
int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
{
cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
-
+
cortex_m3_init_arch_info(target, cortex_m3, target->tap);
-
+
return ERROR_OK;
}
@@ -1613,12 +1613,12 @@ int cortex_m3_register_commands(struct c
{
int retval;
command_t *cortex_m3_cmd;
-
+
retval = armv7m_register_commands(cmd_ctx);
-
- cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands");
+
+ cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands");
register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']");
-
+
return retval;
}
@@ -1627,13 +1627,13 @@ int handle_cortex_m3_mask_interrupts_com
target_t *target = get_current_target(cmd_ctx);
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
if (argc > 0)
{
if (!strcmp(args[0], "on"))
@@ -1649,9 +1649,9 @@ int handle_cortex_m3_mask_interrupts_com
command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']");
}
}
-
+
command_print(cmd_ctx, "cortex_m3 interrupt mask %s",
(cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
-
+
return ERROR_OK;
}
--- a/src/target/target_request.c
+++ b/src/target/target_request.c
@@ -41,25 +41,25 @@ static int target_asciimsg(target_t *tar
{
char *msg = malloc(CEIL(length + 1, 4) * 4);
debug_msg_receiver_t *c = target->dbgmsg;
-
+
target->type->target_request_data(target, CEIL(length, 4), (u8*)msg);
msg[length] = 0;
-
+
LOG_DEBUG("%s", msg);
-
+
while (c)
{
command_print(c->cmd_ctx, "%s", msg);
c = c->next;
}
-
+
return ERROR_OK;
}
static int target_charmsg(target_t *target, u8 msg)
{
LOG_USER_N("%c", msg);
-
+
return ERROR_OK;
}
@@ -70,7 +70,7 @@ static int target_hexmsg(target_t *targe
int line_len;
debug_msg_receiver_t *c = target->dbgmsg;
u32 i;
-
+
LOG_DEBUG("size: %i, length: %i", size, length);
target->type->target_request_data(target, CEIL(length * size, 4), (u8*)data);
@@ -90,11 +90,11 @@ static int target_hexmsg(target_t *targe
line_len += snprintf(line + line_len, 128 - line_len, "%2.2x ", data[i]);
break;
}
-
+
if ((i%8 == 7) || (i == length - 1))
{
LOG_DEBUG("%s", line);
-
+
while (c)
{
command_print(c->cmd_ctx, "%s", line);
@@ -104,7 +104,7 @@ static int target_hexmsg(target_t *targe
line_len = 0;
}
}
-
+
free(data);
return ERROR_OK;
@@ -146,14 +146,14 @@ int target_request(target_t *target, u32
LOG_ERROR("unknown target request: %2.2x", target_req_cmd);
break;
}
-
+
return ERROR_OK;
}
static int add_debug_msg_receiver(struct command_context_s *cmd_ctx, target_t *target)
{
debug_msg_receiver_t **p = &target->dbgmsg;
-
+
if (target == NULL)
return ERROR_INVALID_ARGUMENTS;
@@ -171,10 +171,10 @@ static int add_debug_msg_receiver(struct
(*p) = malloc(sizeof(debug_msg_receiver_t));
(*p)->cmd_ctx = cmd_ctx;
(*p)->next = NULL;
-
+
/* enable callback */
target->dbg_msg_enabled = 1;
-
+
return ERROR_OK;
}
@@ -182,7 +182,7 @@ static debug_msg_receiver_t* find_debug_
{
int do_all_targets = 0;
debug_msg_receiver_t **p = &target->dbgmsg;
-
+
/* if no target has been specified search all of them */
if (target == NULL)
{
@@ -193,7 +193,7 @@ static debug_msg_receiver_t* find_debug_
target = all_targets;
do_all_targets = 1;
}
-
+
do
{
while (*p)
@@ -204,10 +204,10 @@ static debug_msg_receiver_t* find_debug_
}
p = &((*p)->next);
}
-
+
target = target->next;
} while (target && do_all_targets);
-
+
return NULL;
}
@@ -216,14 +216,14 @@ int delete_debug_msg_receiver(struct com
debug_msg_receiver_t **p;
debug_msg_receiver_t *c;
int do_all_targets = 0;
-
+
/* if no target has been specified search all of them */
if (target == NULL)
{
/* if no targets haven been specified */
if (all_targets == NULL)
return ERROR_OK;
-
+
target = all_targets;
do_all_targets = 1;
}
@@ -250,10 +250,10 @@ int delete_debug_msg_receiver(struct com
p = &(c->next);
c = next;
}
-
+
target = target->next;
} while (target && do_all_targets);
-
+
return ERROR_OK;
}
@@ -262,7 +262,7 @@ static int handle_target_request_debugms
target_t *target = get_current_target(cmd_ctx);
int receiving = 0;
-
+
/* see if reciever is already registered */
if (find_debug_msg_receiver(cmd_ctx, target) != NULL)
receiving = 1;
@@ -293,7 +293,7 @@ static int handle_target_request_debugms
command_print(cmd_ctx, "usage: target_request debugmsgs ['enable'|'disable'|'charmsg']");
}
}
-
+
command_print(cmd_ctx, "receiving debug messages from current target %s",
(receiving) ? (charmsg_mode?"charmsg":"enabled") : "disabled" );
return ERROR_OK;
@@ -303,7 +303,7 @@ int target_request_register_commands(str
{
target_request_cmd =
register_command(cmd_ctx, NULL, "target_request", NULL, COMMAND_ANY, "target_request commands");
-
+
register_command(cmd_ctx, target_request_cmd, "debugmsgs", handle_target_request_debugmsgs_command,
COMMAND_EXEC, "enable/disable reception of debug messages from target");
_______________________________________________
Openocd-development mailing list
Openocd-development@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/openocd-development
