On Thursday 07 May 2009, Magnus Lundin wrote: > > Which suggested a potential workaround here: slow TCK down even > > more. Sure enough, at 750 KHz the startup doesn't fail... > > Is it possible to increase the jtag speed after the inital scan chain > identification has succeded at 750 khz?
To 1.5 MHz, yes. To 3 MHz, no (and that has previously worked, with older SVN and also with URjtag): Error: BUG: unknown debug reason: 0xf Does that suggest anything? I've not yet put together code to set up the PLLs; once that's done, I would expect these symptoms to disappear since the chip will mostly be running at over 200 MHz, not just 24 MHz. (The max jtag clock for these chips is 50 MHz, although the ft2232 adapters can't go that high.) - Dave _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
