Hi Dirk Very good, I think we can commit this immediatleay as a place to collect the info about A8. I now have a BeagleBoard :), so testing can be made more efficient, JTAG solution will be working at the end of the week, strange pinout and low voltage.
The magic sequence for unlocking debug registers in the core power domain is # Unlock debug register modification access mww 0x54011FB0 0xC5ACCE55 # Clear Sticky Power Down status Bit mdw 0x54011314 # Check that it is cleared mdw 0x54011314 # Now we can read Core Debug Registers at offset 0x080 mdw 0x54011080 4 This works for me with UBoot running, perhaps the Linux kernel will change some settings, we will see .. Regards, Magnus Dirk Behme wrote: > > Patch in attachment is a minimalist copy of Cortex M3 code to be able > to create a Cortex A8 target and use it for our OMAP3 investigation (*). > > Idea is to extend this step by step with increasing knowledge. > > Many thanks to Magnus for all the help with OMAP3! > > Best regards > Dirk > > (*) Commands that work with this e.g.: > > -- cut -- > > jtag tapenable omap3.cpu > Enabling Cortex-A8 @ OMAP3 > Cortex-A8 @ OMAP3 enabled > 1 > > target create omap3.cpu cortex_a8 -endian little -chain-position > omap3.cpu > > > targets > CmdName Type Endian AbsChainPos Name State > -- ---------- ---------- ---------- ----------- ------------- ---------- > 0: omap3.cpu cortex_a8 little 0 omap3.cpu unknown > > > dap apsel 1 > ap 1 selected, identification register 0x04770002 > > > omap3.cpu mdw 0x54011d00 > 0x54011d00 411fc082 ...A > > > dap info 1 > ap identification register 0x04770002 > Type is mem-ap APB > ap debugbase 0x80000000 > ROM table in legacy format > CID3 0xb1, CID2 0x5, CID1 0x10, CID0, 0xd > MEMTYPE system memory not present. Dedicated debug bus > ROMTABLE[0x0] = 0xd4010003 > Component base address 0x54010000, pid4 0x4, start > address 0x54010000 > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x10, PID2 0x2b, PID1 0xb9, PID0, 0x21 > ROMTABLE[0x4] = 0xd4011003 > Component base address 0x54011000, pid4 0x4, start > address 0x54011000 > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x10, PID2 0x2b, PID1 0xbc, PID0, 0x8 > ROMTABLE[0x8] = 0xd4012003 > Component base address 0x54012000, pid4 0x0, start > address 0x54012000 > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0x9, PID1 0x71, PID0, 0x13 > ROMTABLE[0xc] = 0xd4013002 > Component not present > ROMTABLE[0x10] = 0xd4019003 > Component base address 0x54019000, pid4 0x4, start > address 0x54019000 > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0x1b, PID1 0xb9, PID0, 0x12 > ROMTABLE[0x14] = 0xd401b003 > Component base address 0x5401b000, pid4 0x4, start > address 0x5401b000 > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0xb, PID1 0xb9, PID0, 0x7 > ROMTABLE[0x18] = 0xd401d003 > Component base address 0x5401d000, pid4 0x0, start > address 0x5401d000 > Component cid1 0xf0, class is Non standard layout > CID3 0xb1, CID2 0x5, CID1 0xf0, CID0, 0xd > PID3 0x0, PID2 0x9, PID1 0x73, PID0, 0x43 > ROMTABLE[0x1c] = 0xd4500003 > Component base address 0x54500000, pid4 0x0, start > address 0x54500000 > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0x19, PID1 0x71, PID0, 0x20 > ROMTABLE[0x20] = 0x0 > End of ROM table > -- cut -- _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
