tangray wrote:
> Trying to access Debug Reister Interface with mdw I get
>
>
>
>
>
>> omap3.cpu mdw 0x54011d00
>>
>
>
> 0x54011d00 411fc082 ...A
>
> Looking at Cortex-A8 TRM, it seems OK.
>
>
>
>
>> omap3.cpu mdw 0x54011088
>>
>
> AHBAP Cached values: dp_select 0x0, ap_csw 0xc3800042, ap_tar 0x54011088
>
> SWJ-DP STICKY ERROR
>
> Read MEM_AP_CSW 0x43800042, MEM_AP_TAR 0x54011088
>
> AHBAP Cached values: dp_select 0x0, ap_csw 0xc3800042, ap_tar 0x54011088
>
> SWJ-DP STICKY ERROR
>
> Read MEM_AP_CSW 0x43800042, MEM_AP_TAR 0x54011088
>
> Block read error address 0x54011088, count 0x1
>
> Runtime error, file "command.c", line 456:
>
> error reading target @ 0x54011088
>
>
>
Look at Cortex-A8 TRM table 12-3, the registers that works are the ones that
are
in the Debug power domain, the others are in the Core power domain.
STICKY errors are signals of a bus or access error, so registers in the
Debug power domain are connected/powered/accesible from the MEM-AP and the ones
in the Core power domain are not.
On page 12-53 we find the following:
-------------------------
Note
On system reset, PRSR[1] resets to 1. Table 12-6 on page 12-15 specified
that if PRSR[1] is set to 1, then accessing any register in the core power
domain results in an error response. For these reasons, the debugger cannot
access any
register in the core power domain unless the debugger clears PRSR[1] to 0.
-------------------------
PRSR is at offset 0x314, the sticky bits are cleared by just reading
this register, try it twice :)
Regards,
Magnus
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