7 files from the \src\target\target\ should actually be placed in
\src\target\board\ directory, as they are for evaluation kits or are not
a pure chip description. Attached patch removes them from the target
subdir, and places them in the board subdir, with some name changes to
describe the manufacturer and the full name.
4\/3!!
Index: src/target/board/digi_connectcore_wi-9c.cfg
===================================================================
--- src/target/board/digi_connectcore_wi-9c.cfg (revision 0)
+++ src/target/board/digi_connectcore_wi-9c.cfg (revision 0)
@@ -0,0 +1,128 @@
+# FIXME: THIS IS A *BOARD* not a CHIP configuration.
+######################################
+# Target: DIGI ConnectCore Wi-9C
+######################################
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN big
+}
+
+
+# What's a good fallback frequency for this board if RCLK is
+# not available??
+jtag_rclk 1000
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xFFFFFFFF
+}
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap_device $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 0
+
+
+######################
+# Target configuration
+######################
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -event reset-init {
+ mww 0x90600104 0x33313333
+ mww 0xA0700000 0x00000001 # Enable the memory controller.
+ mww 0xA0700024 0x00000006 # Set the refresh counter 6
+ mww 0xA0700028 0x00000001 #
+ mww 0xA0700030 0x00000001 # Set the precharge period
+ mww 0xA0700034 0x00000004 # Active to precharge command period is 16
clock cycles
+ mww 0xA070003C 0x00000001 # tAPR
+ mww 0xA0700040 0x00000005 # tDAL
+ mww 0xA0700044 0x00000001 # tWR
+ mww 0xA0700048 0x00000006 # tRC 32 clock cycles
+ mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
+ mww 0xA0700054 0x00000001 # tRRD
+ mww 0xA0700058 0x00000001 # tMRD
+ mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
+ mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
+ mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
+ mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
+ #
+ mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
+ #
+ mww 0xA0700020 0x00000103 # issue SDRAM PALL command
+ #
+ mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as
possible
+ #
+ # Add some dummy writes to give the SDRAM time to settle, it needs two
+ # AHB clock cycles, here we poke in the debugger flag, this lets
+ # the software know that we are in the debugger
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ #
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ #
+ mww 0xA0700024 0x00000030 # Set the refresh counter to 30
+ mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
+ #
+ # Next we perform a read of RAM.
+ # mw = move word.
+ mdw 0x00022000
+ # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
+ #
+ mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
+ mww 0xA0700100 0x00084280 # Enable buffer access
+ mww 0xA0700120 0x00084280 # Enable buffer access
+ mww 0xA0700140 0x00084280 # Enable buffer access
+ mww 0xA0700160 0x00084280 # Enable buffer access
+
+ #Set byte lane state (static mem 1)"
+ mww 0xA0700220, 0x00000082
+ #Flash Start
+ mww 0xA09001F8, 0x50000000
+ #Flash Mask Reg
+ mww 0xA09001FC, 0xFF000001
+ mww 0xA0700028, 0x00000001
+
+ # RAMAddr = 0x00020000
+ # RAMSize = 0x00004000
+
+ # Set the processor mode
+ reg cpsr 0xd3
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000
-work-area-size 0x1000 -work-area-backup 1
+
+#####################
+# Flash configuration
+#####################
+
+#M29DW323DB - not working
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x50000000 0x0400000 2 2 0
+
+
+
Index: src/target/board/hitex_stm32-performancestick.cfg
===================================================================
--- src/target/board/hitex_stm32-performancestick.cfg (revision 0)
+++ src/target/board/hitex_stm32-performancestick.cfg (revision 0)
@@ -0,0 +1,50 @@
+# Hitex stm32 performance stick
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32_hitex
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# set jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+# The CPU
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+
+# The boundery scan register, leave the "expected-id" undefined.
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
+
+# configure str750 connected to jtag chain
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
$_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000
-work-area-size 16384 -work-area-backup 0
+
+#
+flash bank stm32x 0 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
Index: src/target/board/hitex_str9-comstick.cfg
===================================================================
--- src/target/board/hitex_str9-comstick.cfg (revision 0)
+++ src/target/board/hitex_str9-comstick.cfg (revision 0)
@@ -0,0 +1,65 @@
+#Hitex STR9 Comstick
+
+# set jtag speed
+jtag_khz 3000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id
$_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id
$_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm966e
+
+$_TARGETNAME configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ #jtag_rclk 3000
+
+ # -- Enable 96K RAM
+ # PFQBC enabled / DTCM & AHB wait-states disabled
+ mww 0x5C002034 0x0191
+
+ str9x flash_config 0 4 2 0 0x80000
+ flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000
-work-area-size 16384 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
Index: src/target/board/linksys_nslu2.cfg
===================================================================
--- src/target/board/linksys_nslu2.cfg (revision 0)
+++ src/target/board/linksys_nslu2.cfg (revision 0)
@@ -0,0 +1,8 @@
+# This is for the LinkSys (CISCO) NSLU2 board
+# It is an Intel XSCALE IXP420 CPU.
+
+source [find target/ixp42x.cfg]
+# The _TARGETNAME is set by the above.
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000
-work-area-size 0x10000 -work-area-backup 0
+
Index: src/target/board/pxa255_sst.cfg
===================================================================
--- src/target/board/pxa255_sst.cfg (revision 0)
+++ src/target/board/pxa255_sst.cfg (revision 0)
@@ -0,0 +1,15 @@
+# A PXA255 test board with SST 39LF400A flash
+#
+# At reset the memory map is as follows. Note that
+# the memory map changes later on as the application
+# starts...
+#
+# RAM at 0x4000000
+# Flash at 0x00000000
+#
+source [find target/pxa255.cfg]
+# Target name is set by above
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000
-work-area-size 0x4000 -work-area-backup 0
+# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum>
[options]
+flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
+
Index: src/target/board/str910-eval.cfg
===================================================================
--- src/target/board/str910-eval.cfg (revision 0)
+++ src/target/board/str910-eval.cfg (revision 0)
@@ -0,0 +1,61 @@
+# str910-eval eval board
+#
+# Need reset scripts
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id
$_FLASHTAPID
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id
$_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm966e
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000
-work-area-size 16384 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ #jtag_rclk 3000
+
+ # -- Enable 96K RAM
+ # PFQBC enabled / DTCM & AHB wait-states disabled
+ mww 0x5C002034 0x0191
+
+ str9x flash_config 0 4 2 0 0x80000
+ flash protect 0 0 7 off
+}
+
+#flash bank str9x <base> <size> 0 0 <target#> <variant>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
Index: src/target/board/zy1000.cfg
===================================================================
--- src/target/board/zy1000.cfg (revision 0)
+++ src/target/board/zy1000.cfg (revision 0)
@@ -0,0 +1,110 @@
+#Script for ZY1000
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME zy1000
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi-s_r4
+
+# at CPU CLK <32kHz this must be disabled
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+$_TARGETNAME configure -event reset-init {
+ # Set up chip selects & timings
+ mww 0xFFE00000 0x0100273D
+ mww 0xFFE00004 0x08002125
+ mww 0xFFEe0008 0x02002125
+ mww 0xFFE0000c 0x03002125
+ mww 0xFFE00010 0x40000000
+ mww 0xFFE00014 0x50000000
+ mww 0xFFE00018 0x60000000
+ mww 0xFFE0001c 0x70000000
+ mww 0xFFE00020 0x00000001
+ mww 0xFFE00024 0x00000000
+
+ # remap
+ mww 0xFFFFF124 0xFFFFFFFF
+ mww 0xffff0010 0x100
+ mww 0xffff0034 0x100
+
+ #disable 16x5x UART interrupts
+ mww 0x08020004 0
+}
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000
-work-area-size 0x20000 -work-area-backup 0
+
+jtag_khz 16000
+
+
+proc production_info {} {
+ return "Serial number is official MAC number. Format XXXXXXXXXXXX"
+}
+
+# There is no return value from this procedure. If it is
+# successful it does not throw an exception
+#
+# Progress messages are output via puts
+proc production {firmwarefile serialnumber} {
+ if {[string length $serialnumber]!=12} {
+ puts "Invalid serial number"
+ return
+ }
+
+ puts "Power cycling target"
+ power off
+ sleep 3000
+ power on
+ sleep 1000
+ reset init
+ flash write_image erase $firmwarefile 0x1000000 bin
+ verify_image $firmwarefile 0x1000000 bin
+
+ # Big endian... weee!!!!
+ puts "Setting MAC number to $serialnumber"
+ flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2
3][string range $serialnumber 0 1]0000" 1
+ flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10
11][string range $serialnumber 8 9][string range $serialnumber 6 7][string
range $serialnumber 4 5]" 1
+ puts "Production successful"
+}
+
+
+proc production_test {} {
+ power on
+ sleep 1000
+ target_request debugmsgs enable
+ reset run
+ sleep 25000
+ target_request debugmsgs disable
+ return "See IP address above..."
+}
Index: src/target/target/nslu2.cfg
===================================================================
--- src/target/target/nslu2.cfg (revision 1454)
+++ src/target/target/nslu2.cfg (working copy)
@@ -1,8 +0,0 @@
-# This is for the LinkSys (CISCO) NSLU2 board
-# It is an Intel XSCALE IXP420 CPU.
-
-source [find target/ixp42x.cfg]
-# The _TARGETNAME is set by the above.
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000
-work-area-size 0x10000 -work-area-backup 0
-
Index: src/target/target/pxa255_sst.cfg
===================================================================
--- src/target/target/pxa255_sst.cfg (revision 1454)
+++ src/target/target/pxa255_sst.cfg (working copy)
@@ -1,15 +0,0 @@
-# A PXA255 test board with SST 39LF400A flash
-#
-# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application
-# starts...
-#
-# RAM at 0x4000000
-# Flash at 0x00000000
-#
-source [find target/pxa255.cfg]
-# Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000
-work-area-size 0x4000 -work-area-backup 0
-# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum>
[options]
-flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-
Index: src/target/target/stm32stick.cfg
===================================================================
--- src/target/target/stm32stick.cfg (revision 1454)
+++ src/target/target/stm32stick.cfg (working copy)
@@ -1,50 +0,0 @@
-# Hitex stm32 performance stick
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32_hitex
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# set jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-# The CPU
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.3
- set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
-
-# The boundery scan register, leave the "expected-id" undefined.
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
-
-# configure str750 connected to jtag chain
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
$_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000
-work-area-size 16384 -work-area-backup 0
-
-#
-flash bank stm32x 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
Index: src/target/target/str910-eval.cfg
===================================================================
--- src/target/target/str910-eval.cfg (revision 1454)
+++ src/target/target/str910-eval.cfg (working copy)
@@ -1,61 +0,0 @@
-# str910-eval eval board
-#
-# Need reset scripts
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id
$_FLASHTAPID
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id
$_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm966e
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000
-work-area-size 16384 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
Index: src/target/target/str9comstick.cfg
===================================================================
--- src/target/target/str9comstick.cfg (revision 1454)
+++ src/target/target/str9comstick.cfg (working copy)
@@ -1,65 +0,0 @@
-#Hitex STR9 Comstick
-
-# set jtag speed
-jtag_khz 3000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id
$_FLASHTAPID
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id
$_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000
-work-area-size 16384 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
Index: src/target/target/wi-9c.cfg
===================================================================
--- src/target/target/wi-9c.cfg (revision 1454)
+++ src/target/target/wi-9c.cfg (working copy)
@@ -1,128 +0,0 @@
-# FIXME: THIS IS A *BOARD* not a CHIP configuration.
-######################################
-# Target: DIGI ConnectCore Wi-9C
-######################################
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ns9360
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN big
-}
-
-
-# What's a good fallback frequency for this board if RCLK is
-# not available??
-jtag_rclk 1000
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0xFFFFFFFF
-}
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap_device $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
-
-
-######################
-# Target configuration
-######################
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -event reset-init {
- mww 0x90600104 0x33313333
- mww 0xA0700000 0x00000001 # Enable the memory controller.
- mww 0xA0700024 0x00000006 # Set the refresh counter 6
- mww 0xA0700028 0x00000001 #
- mww 0xA0700030 0x00000001 # Set the precharge period
- mww 0xA0700034 0x00000004 # Active to precharge command period is 16
clock cycles
- mww 0xA070003C 0x00000001 # tAPR
- mww 0xA0700040 0x00000005 # tDAL
- mww 0xA0700044 0x00000001 # tWR
- mww 0xA0700048 0x00000006 # tRC 32 clock cycles
- mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
- mww 0xA0700054 0x00000001 # tRRD
- mww 0xA0700058 0x00000001 # tMRD
- mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
- mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
- mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
- mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
- #
- mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
- #
- mww 0xA0700020 0x00000103 # issue SDRAM PALL command
- #
- mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as
possible
- #
- # Add some dummy writes to give the SDRAM time to settle, it needs two
- # AHB clock cycles, here we poke in the debugger flag, this lets
- # the software know that we are in the debugger
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- #
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- #
- mww 0xA0700024 0x00000030 # Set the refresh counter to 30
- mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
- #
- # Next we perform a read of RAM.
- # mw = move word.
- mdw 0x00022000
- # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
- #
- mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
- mww 0xA0700100 0x00084280 # Enable buffer access
- mww 0xA0700120 0x00084280 # Enable buffer access
- mww 0xA0700140 0x00084280 # Enable buffer access
- mww 0xA0700160 0x00084280 # Enable buffer access
-
- #Set byte lane state (static mem 1)"
- mww 0xA0700220, 0x00000082
- #Flash Start
- mww 0xA09001F8, 0x50000000
- #Flash Mask Reg
- mww 0xA09001FC, 0xFF000001
- mww 0xA0700028, 0x00000001
-
- # RAMAddr = 0x00020000
- # RAMSize = 0x00004000
-
- # Set the processor mode
- reg cpsr 0xd3
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000
-work-area-size 0x1000 -work-area-backup 1
-
-#####################
-# Flash configuration
-#####################
-
-#M29DW323DB - not working
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
-
-
-
Index: src/target/target/zy1000.cfg
===================================================================
--- src/target/target/zy1000.cfg (revision 1454)
+++ src/target/target/zy1000.cfg (working copy)
@@ -1,110 +0,0 @@
-#Script for ZY1000
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME zy1000
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi-s_r4
-
-# at CPU CLK <32kHz this must be disabled
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init {
- # Set up chip selects & timings
- mww 0xFFE00000 0x0100273D
- mww 0xFFE00004 0x08002125
- mww 0xFFEe0008 0x02002125
- mww 0xFFE0000c 0x03002125
- mww 0xFFE00010 0x40000000
- mww 0xFFE00014 0x50000000
- mww 0xFFE00018 0x60000000
- mww 0xFFE0001c 0x70000000
- mww 0xFFE00020 0x00000001
- mww 0xFFE00024 0x00000000
-
- # remap
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-
- #disable 16x5x UART interrupts
- mww 0x08020004 0
-}
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000
-work-area-size 0x20000 -work-area-backup 0
-
-jtag_khz 16000
-
-
-proc production_info {} {
- return "Serial number is official MAC number. Format XXXXXXXXXXXX"
-}
-
-# There is no return value from this procedure. If it is
-# successful it does not throw an exception
-#
-# Progress messages are output via puts
-proc production {firmwarefile serialnumber} {
- if {[string length $serialnumber]!=12} {
- puts "Invalid serial number"
- return
- }
-
- puts "Power cycling target"
- power off
- sleep 3000
- power on
- sleep 1000
- reset init
- flash write_image erase $firmwarefile 0x1000000 bin
- verify_image $firmwarefile 0x1000000 bin
-
- # Big endian... weee!!!!
- puts "Setting MAC number to $serialnumber"
- flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2
3][string range $serialnumber 0 1]0000" 1
- flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10
11][string range $serialnumber 8 9][string range $serialnumber 6 7][string
range $serialnumber 4 5]" 1
- puts "Production successful"
-}
-
-
-proc production_test {} {
- power on
- sleep 1000
- target_request debugmsgs enable
- reset run
- sleep 25000
- target_request debugmsgs disable
- return "See IP address above..."
-}
_______________________________________________
Openocd-development mailing list
Openocd-development@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/openocd-development
