On Wed, Nov 19, 2008 at 9:41 PM, Kees Jongenburger
<[EMAIL PROTECTED]> wrote:
> On Sat, Nov 8, 2008 at 7:10 PM, David Anders <[EMAIL PROTECTED]> wrote:
>> any changes/development we do to support JRC's can be tested currently with
>> the DM-355 and >related davinci boards, as they already have debug support
>> in the main tree >of openocd. this >gives you a reference for testing.
>
> Hello
>
> I am trying to make some progress on the beagleboard front. I started
> implementing
> a jcr_icepick target that would give control over the icepick. I would
> value your input(code wise) as it looks crap to me :p.
> the goal currently is to implement the icepick commands and perform a
> new "examine scan chain"
> afterwards to see that there are more items in the scan chain.
>
> the diff is against r1176.
>
> Greetings
>
now with attachment..
Index: src/target/target/omap35xx.cfg
===================================================================
--- src/target/target/omap35xx.cfg (revision 0)
+++ src/target/target/omap35xx.cfg (revision 0)
@@ -0,0 +1,8 @@
+#Basic configuration for the omap35xx series
+
+#jtag scan chain
+#the first item is the IcePick.
+jtag_device 6 0x1 0x0 0x0
+
+
+target create target0 jrc_icepick -chain-position 0
Index: src/target/target.c
===================================================================
--- src/target/target.c (revision 1177)
+++ src/target/target.c (working copy)
@@ -106,6 +106,7 @@
extern target_type_t cortexm3_target;
extern target_type_t arm11_target;
extern target_type_t mips_m4k_target;
+extern target_type_t jrc_icepick_target;
target_type_t *target_types[] =
{
@@ -120,6 +121,7 @@
&cortexm3_target,
&arm11_target,
&mips_m4k_target,
+ &jrc_icepick_target,
NULL,
};
Index: src/target/jrc_icepick.c
===================================================================
--- src/target/jrc_icepick.c (revision 0)
+++ src/target/jrc_icepick.c (revision 0)
@@ -0,0 +1,182 @@
+/***************************************************************************
+ * Copyright (C) 2008 Kees Jongenburger *
+ * [EMAIL PROTECTED] *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+#include "target.h"
+#include <unistd.h>
+#include "jrc_icepick.h"
+
+#include "log.h" /* We need this to have ERROR_OK ....*/
+#include "jtag.h"
+
+target_type_t jrc_icepick_target =
+{
+ /* The reqired fields */
+ .name = "jrc_icepick",
+ .init_target = jrc_icepick_init_target,
+ .poll = jrc_icepick_poll,
+ .examine = jrc_icepick_examine,
+};
+
+/* define the jrc target type as used in target.c */
+int jrc_icepick_init_target(struct command_context_s *cmd_ctc, struct target_s *target)
+{
+ return ERROR_OK; /* success */
+};
+
+int jrc_icepick_poll(struct target_s *target)
+{
+ return ERROR_OK; /* success */
+}
+/* examine the item in the chain to see if it is an icepick */
+int jrc_icepick_examine(struct target_s *target){
+ scan_field_t ir_field;
+ scan_field_t ir_field_2;
+ scan_field_t ir_field_3;
+ scan_field_t dr_field;
+ scan_field_t dr_field_2;
+ scan_field_t dr_field_3;
+ scan_field_t dr_field_4;
+ scan_field_t dr_field_5;
+ u8 dr_data;
+ u32 dr_data_2;
+ u32 dr_data_3;
+ u32 dr_data_4;
+ u32 dr_data_5;
+
+ LOG_DEBUG("IcePick is number %i in the chain",target->chain_position);
+
+ /* irscan 0 7 */
+ ir_field.device = target->chain_position; /* 1 */
+ ir_field.num_bits = 6;
+ ir_field.out_value = calloc(CEIL(ir_field.num_bits, 8), 1);
+ buf_set_u32(ir_field.out_value, 0, ir_field.num_bits, 0x07);
+ ir_field.out_mask = NULL;
+ ir_field.in_value = NULL;
+ ir_field.in_check_value = NULL;
+ ir_field.in_check_mask = NULL;
+ ir_field.in_handler = NULL;
+ ir_field.in_handler_priv = NULL;
+ jtag_add_ir_scan(1, &ir_field, end_state); /* where does end_state come from */
+
+
+ /* drscan 0 8 0X89 */
+ dr_data= 0x89;
+ dr_field.device = target->chain_position; /* 1 */
+ dr_field.num_bits = 8;
+ dr_field.out_value = NULL;
+ dr_field.out_mask = NULL;
+ dr_field.in_value = &dr_data; /* Do I need to use the buf_set_u32 and have order reversed? */
+ dr_field.in_check_value = NULL;
+ dr_field.in_check_mask = NULL;
+ dr_field.in_handler = NULL;
+ dr_field.in_handler_priv = NULL;
+ jtag_add_dr_scan(1, &dr_field, TAP_RTI);
+
+ /* irscan 0 2 */
+ ir_field_2.device = target->chain_position; /* 1 */
+ ir_field_2.num_bits = 6;
+ ir_field_2.out_value = calloc(CEIL(ir_field_2.num_bits, 8), 1);
+ buf_set_u32(ir_field_2.out_value, 0, ir_field_2.num_bits, 0x02);
+ ir_field_2.out_mask = NULL;
+ ir_field_2.in_value = NULL;
+ ir_field_2.in_check_value = NULL;
+ ir_field_2.in_check_mask = NULL;
+ ir_field_2.in_handler = NULL;
+ ir_field_2.in_handler_priv = NULL;
+ jtag_add_ir_scan(1, &ir_field_2, end_state);
+
+ /* drscan 0 32 0x81000080 */
+ dr_data_2= 0x81000080;
+ dr_field_2.device = target->chain_position; /* 1 */
+ dr_field_2.num_bits = 32;
+ dr_field_2.out_value = NULL;
+ dr_field_2.out_mask = NULL;
+ dr_field_2.in_value = &dr_data_2; /* same here is the order OK? */
+ dr_field_2.in_check_value = NULL;
+ dr_field_2.in_check_mask = NULL;
+ dr_field_2.in_handler = NULL;
+ dr_field_2.in_handler_priv = NULL;
+ jtag_add_dr_scan(1, &dr_field_2, TAP_RTI);
+
+ /* drscan 0 32 0xa3002048 */
+ dr_data_3= 0xa3002048;
+ dr_field_3.device = target->chain_position; /* 1 */
+ dr_field_3.num_bits = 32;
+ dr_field_3.out_value = NULL;
+ dr_field_3.out_mask = NULL;
+ dr_field_3.in_value = &dr_data_3;
+ dr_field_3.in_check_value = NULL;
+ dr_field_3.in_check_mask = NULL;
+ dr_field_3.in_handler = NULL;
+ dr_field_3.in_handler_priv = NULL;
+ jtag_add_dr_scan(1, &dr_field_3, TAP_RTI);
+
+ /* drscan 0 32 0x81000081 */
+ dr_data_4= 0x81000081;
+ dr_field_4.device = target->chain_position; /* 1 */
+ dr_field_4.num_bits = 32;
+ dr_field_4.out_value = NULL;
+ dr_field_4.out_mask = NULL;
+ dr_field_4.in_value = &dr_data_4;
+ dr_field_4.in_check_value = NULL;
+ dr_field_4.in_check_mask = NULL;
+ dr_field_4.in_handler = NULL;
+ dr_field_4.in_handler_priv = NULL;
+ jtag_add_dr_scan(1, &dr_field_4, TAP_RTI);
+
+ /* drscan 0 32 0xa3002148 */
+ dr_data_5= 0xa3002148;
+ dr_field_5.device = target->chain_position; /* 1 */
+ dr_field_5.num_bits = 32;
+ dr_field_5.out_value = NULL;
+ dr_field_5.out_mask = NULL;
+ dr_field_5.in_value = &dr_data_5;
+ dr_field_5.in_check_value = NULL;
+ dr_field_5.in_check_mask = NULL;
+ dr_field_5.in_handler = NULL;
+ dr_field_5.in_handler_priv = NULL;
+ jtag_add_dr_scan(1, &dr_field_5, TAP_RTI);
+
+ /* irscan 0 0x3f */
+ ir_field_3.device = target->chain_position; /* 1 */
+ ir_field_3.num_bits = 6;
+ ir_field_3.out_value = calloc(CEIL(ir_field.num_bits, 8), 1);
+ buf_set_u32(ir_field.out_value, 0, ir_field.num_bits, 0x3f);
+ ir_field_3.out_mask = NULL;
+ ir_field_3.in_value = NULL;
+ ir_field_3.in_check_value = NULL;
+ ir_field_3.in_check_mask = NULL;
+ ir_field_3.in_handler = NULL;
+ ir_field_3.in_handler_priv = NULL;
+ jtag_add_ir_scan(1, &ir_field_3, end_state); /* where does end_state come from */
+
+ /* execute the commands */
+ jtag_execute_queue();
+
+ usleep(1000); /* portable? */
+
+ free(ir_field.out_value);
+ free(ir_field_2.out_value);
+ free(ir_field_3.out_value);
+
+
+ /* TODO add test to scan the chain */
+ return ERROR_OK; /* success */
+}
Index: src/target/jrc_icepick.h
===================================================================
--- src/target/jrc_icepick.h (revision 0)
+++ src/target/jrc_icepick.h (revision 0)
@@ -0,0 +1,64 @@
+/***************************************************************************
+ * Copyright (C) 2008 Kees Jongenburger *
+ * [EMAIL PROTECTED] *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+#ifndef JRC_ICEPICK_H
+#define JRC_ICEPICK_H
+
+/*
+ * JRC or JTAG Router Controler is a piece hardware that can dynamically
+ * add or remove Test access points to a JTAG scan chain.
+ *
+ * Texas Instruments calls this feature ICEPick. ICEPick can be seen as
+ * Controller with can not only enable and disable parts of the scan chain
+ * but apparently also other things (like reading the emu status bits?).
+ *
+ * JTAG
+ *
+ * TDO | | TDI
+ * | |
+ * -----|------------|---------------
+ * | | | |
+ * | | (Bypass)-IcePickTAP |
+ * | | | |
+ * | (Bypass)-----(Bypass) |
+ * ----------------------------------
+ * | |
+ * | |
+ * CoreSight DSP
+ *
+ *
+ * Sample openocd command to add the core to the scan chain(not working)
+ * irscan 0 7
+ * drscan 0 8 0X89
+ * irscan 0 2
+ * drscan 0 32 0x81000080
+ * drscan 0 32 0xa3002048
+ * drscan 0 32 0x81000081
+ * drscan 0 32 0xa3002148
+ * sleep 10
+ * jtag_device 4 0x1 0x0 0xe
+ */
+
+/* target type methods */
+int jrc_icepick_init_target(struct command_context_s *cmd_ctc, struct target_s *target);
+int jrc_icepick_poll(struct target_s *target);
+int jrc_icepick_examine(struct target_s *target);
+
+#endif /* JRC_ICEPICK_H */
Index: src/target/Makefile.am
===================================================================
--- src/target/Makefile.am (revision 1177)
+++ src/target/Makefile.am (working copy)
@@ -13,11 +13,12 @@
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
- mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
+ mips32_pracc.c mips32_dmaacc.c mips_ejtag.c jrc_icepick.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
- etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
+ etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h \
+ jrc_icepick.h
nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
target/at91r40008.cfg target/lpc2148.cfg target/lpc2148_rclk.cfg target/lpc2148_2mhz.cfg target/lpc2294.cfg \
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