Hi,
here is the whitespace corrected and attached patch. I also reduced the
retries from 16 to 4. I plan to get rid of them entirely eventually.
Cheers,
John McC.
On Tue, 2008-10-07 at 07:43 +0100, Spen wrote:
> John,
>
> >
> > The following patch adds support for DMA mode access as
> > supported by EJTAG 1.0/2.0 processors, specifically the
> > Broadcom BCM5352 (and BCM47xx) SoC processors used in the
> > Linksys WRT54G series of wireless routers.
> > This is needed because PrAcc mode seems non-functional on
> > these chips. I have a theory on why this but believe WRT54GL
> > firmware changes are necessary to get it working (unlike
> > later EJTAG versions I don't think ProbeTrap is implemented).
> > In any case I've been unable to get PrAcc to work with this
> > processor.
> >
> > The DMA read/write logic comes from the wrt54g_debrick flash
> > utility for the WRT54 series by HairyDairyMaid. I plan to
> > clean it up (don't think the retries are the right thing to
> > do) but this is a good start that works for me on my WRT54GL
> > with a BCM5352.
> > I can now read/write memory and program the flash of my
> > WRT54GL with OpenOCD (though it is pretty slow to
> > program--I'm working on improving that).
> >
> > This mode is enabled if the EJTAG impcode indicates that DMA
> > mode is available which I believe is just EJTAG 1.0/2.0 processors.
> >
> >
> > Enjoy,
> > John McCarthy.
> >
>
> This patch initially looks ok, could you send as a attachment and reformat
> the spaces to tab chars.
>
> Cheers
> Spen
>
>
Date: Sun, 5 Oct 2008 21:16:10 -0400
Subject: [PATCH] Add support for EJTAG 1.0/2.0 DMA mode memory accesses.
- also add LOG_DEBUG decoding of impcode and failure to enter debug mode.
Signed-off-by: John McCarthy <[EMAIL PROTECTED]>
---
Index: src/target/mips_ejtag.c
===================================================================
--- src/target/mips_ejtag.c (revision 1022)
+++ src/target/mips_ejtag.c (working copy)
@@ -204,6 +204,9 @@
/* break bit will be cleared by hardware */
ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+ LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
+ if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+ LOG_DEBUG("Failed to enter Debug Mode!");
return ERROR_OK;
}
@@ -275,6 +278,17 @@
LOG_DEBUG("EJTAG: Unknown Version Detected");
break;
}
+ LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
+ ejtag_info->impcode & (1<<28) ? " R3k": " R4k",
+ ejtag_info->impcode & (1<<24) ? " DINT": "",
+ ejtag_info->impcode & (1<<22) ? " ASID_8": "",
+ ejtag_info->impcode & (1<<21) ? " ASID_6": "",
+ ejtag_info->impcode & (1<<16) ? " MIPS16": "",
+ ejtag_info->impcode & (1<<14) ? " noDMA": " DMA",
+ ejtag_info->impcode & (1<<0) ? " MIPS64": " MIPS32"
+ );
+ if((ejtag_info->impcode & (1<<14)) == 0)
+ LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
/* set initial state for ejtag control reg */
ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
Index: src/target/mips_ejtag.h
===================================================================
--- src/target/mips_ejtag.h (revision 1022)
+++ src/target/mips_ejtag.h (working copy)
@@ -38,7 +38,7 @@
#define EJTAG_INST_TCBCONTROLA 0x10
#define EJTAG_INST_TCBCONTROLB 0x11
#define EJTAG_INST_TCBDATA 0x12
-#define EJTAG_INST_BYPASS 0x1F
+#define EJTAG_INST_BYPASS 0xFF
#define EJTAG_CTRL_TOF (1 << 1)
#define EJTAG_CTRL_TIF (1 << 2)
Index: src/target/mips32_dmaacc.c
===================================================================
--- src/target/mips32_dmaacc.c (revision 0)
+++ src/target/mips32_dmaacc.c (revision 0)
@@ -0,0 +1,441 @@
+/***************************************************************************
+ * Copyright (C) 2008 by John McCarthy *
+ * [EMAIL PROTECTED] *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * [EMAIL PROTECTED] *
+ * *
+ * Copyright (C) 2008 by David T.L. Wong *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <string.h>
+#include "log.h"
+#include "mips32.h"
+#include "mips32_dmaacc.h"
+
+/*
+ * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
+ * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
+ * (and any others that support EJTAG DMA transfers).
+ * Note: This only supports memory read/write. Since the BCM5352 doesn't
+ * appear to support PRACC accesses, all debug functions except halt
+ * do not work. Still, this does allow erasing/writing flash as well as
+ * displaying/modifying memory and memory mapped registers.
+ */
+
+static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
+{
+ u32 v;
+ u32 ctrl_reg;
+ int retries = RETRY_ATTEMPTS;
+
+begin_ejtag_dma_read:
+
+ // Setup Address
+ v = addr;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Initiate DMA Read & set DSTRT
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+
+ // Wait for DSTRT to Clear
+ do {
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+
+ // Read Data
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_drscan_32(ejtag_info, data);
+
+ // Clear DMA & Check DERR
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ if (ctrl_reg & EJTAG_CTRL_DERR)
+ {
+ if (retries--) {
+ printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
+ goto begin_ejtag_dma_read;
+ } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
+{
+ u32 v;
+ u32 ctrl_reg;
+ int retries = RETRY_ATTEMPTS;
+
+begin_ejtag_dma_read_h:
+
+ // Setup Address
+ v = addr;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Initiate DMA Read & set DSTRT
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+
+ // Wait for DSTRT to Clear
+ do {
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+
+ // Read Data
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Clear DMA & Check DERR
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ if (ctrl_reg & EJTAG_CTRL_DERR)
+ {
+ if (retries--) {
+ printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
+ goto begin_ejtag_dma_read_h;
+ } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ // Handle the bigendian/littleendian
+ if ( addr & 0x2 ) *data = (v>>16)&0xffff ;
+ else *data = (v&0x0000ffff) ;
+
+ return ERROR_OK;
+}
+
+static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
+{
+ u32 v;
+ u32 ctrl_reg;
+ int retries = RETRY_ATTEMPTS;
+
+begin_ejtag_dma_read_b:
+
+ // Setup Address
+ v = addr;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Initiate DMA Read & set DSTRT
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+
+ // Wait for DSTRT to Clear
+ do {
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+
+ // Read Data
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Clear DMA & Check DERR
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ if (ctrl_reg & EJTAG_CTRL_DERR)
+ {
+ if (retries--) {
+ printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
+ goto begin_ejtag_dma_read_b;
+ } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ // Handle the bigendian/littleendian
+ switch(addr & 0x3) {
+ case 0: *data = v & 0xff; break;
+ case 1: *data = (v>>8) & 0xff; break;
+ case 2: *data = (v>>16) & 0xff; break;
+ case 3: *data = (v>>24) & 0xff; break;
+ }
+
+ return ERROR_OK;
+}
+
+static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
+{
+ u32 v;
+ u32 ctrl_reg;
+ int retries = RETRY_ATTEMPTS;
+
+begin_ejtag_dma_write:
+
+ // Setup Address
+ v = addr;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Setup Data
+ v = data;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Initiate DMA Write & set DSTRT
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+
+ // Wait for DSTRT to Clear
+ do {
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+
+ // Clear DMA & Check DERR
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ if (ctrl_reg & EJTAG_CTRL_DERR)
+ {
+ if (retries--) {
+ printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
+ goto begin_ejtag_dma_write;
+ } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
+{
+ u32 v;
+ u32 ctrl_reg;
+ int retries = RETRY_ATTEMPTS;
+
+
+ // Handle the bigendian/littleendian
+ data &= 0xffff;
+ data |= data<<16;
+
+begin_ejtag_dma_write_h:
+
+ // Setup Address
+ v = addr;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Setup Data
+ v = data;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Initiate DMA Write & set DSTRT
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+
+ // Wait for DSTRT to Clear
+ do {
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+
+ // Clear DMA & Check DERR
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ if (ctrl_reg & EJTAG_CTRL_DERR)
+ {
+ if (retries--) {
+ printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
+ goto begin_ejtag_dma_write_h;
+ } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
+{
+ u32 v;
+ u32 ctrl_reg;
+ int retries = RETRY_ATTEMPTS;
+
+
+ // Handle the bigendian/littleendian
+ data &= 0xff;
+ data |= data<<8;
+ data |= data<<16;
+
+begin_ejtag_dma_write_b:
+
+ // Setup Address
+ v = addr;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Setup Data
+ v = data;
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &v);
+
+ // Initiate DMA Write & set DSTRT
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+
+ // Wait for DSTRT to Clear
+ do {
+ ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+
+ // Clear DMA & Check DERR
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
+ mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+ if (ctrl_reg & EJTAG_CTRL_DERR)
+ {
+ if (retries--) {
+ printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
+ goto begin_ejtag_dma_write_b;
+ } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+
+int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
+{
+ switch (size)
+ {
+ case 1:
+ return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
+ case 2:
+ return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
+ case 4:
+ return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
+{
+ int i;
+ int retval;
+
+ for(i=0; i<count; i++) {
+ if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
+{
+ int i;
+ int retval;
+
+ for(i=0; i<count; i++) {
+ if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
+{
+ int i;
+ int retval;
+
+ for(i=0; i<count; i++) {
+ if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
+{
+ switch (size)
+ {
+ case 1:
+ return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
+ case 2:
+ return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
+ case 4:
+ return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
+{
+ int i;
+ int retval;
+
+ for(i=0; i<count; i++) {
+ if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
+{
+ int i;
+ int retval;
+
+ for(i=0; i<count; i++) {
+ if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
+{
+ int i;
+ int retval;
+
+ for(i=0; i<count; i++) {
+ if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+ return retval;
+ }
+
+ return ERROR_OK;
+}
Index: src/target/mips32_dmaacc.h
===================================================================
--- src/target/mips32_dmaacc.h (revision 0)
+++ src/target/mips32_dmaacc.h (revision 0)
@@ -0,0 +1,53 @@
+/***************************************************************************
+ * Copyright (C) 2008 by John McCarthy *
+ * [EMAIL PROTECTED] *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * [EMAIL PROTECTED] *
+ * *
+ * Copyright (C) 2008 by David T.L. Wong *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef MIPS32_DMAACC_H
+#define MIPS32_DMAACC_H
+
+#include "mips_ejtag.h"
+
+#define EJTAG_CTRL_DMA_BYTE 0x00000000
+#define EJTAG_CTRL_DMA_HALFWORD 0x00000080
+#define EJTAG_CTRL_DMA_WORD 0x00000100
+#define EJTAG_CTRL_DMA_TRIPLEBYTE 0x00000180
+
+#define RETRY_ATTEMPTS 4
+
+extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
+extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
+
+extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
+extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
+extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
+
+extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
+extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
+extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
+
+#if 0
+extern int mips32_dmaacc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs);
+extern int mips32_dmaacc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs);
+#endif
+
+#endif
Index: src/target/mips_m4k.c
===================================================================
--- src/target/mips_m4k.c (revision 1022)
+++ src/target/mips_m4k.c (working copy)
@@ -512,7 +512,11 @@
case 4:
case 2:
case 1:
- return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
+ /* if noDMA off, use DMAACC mode for memory read */
+ if(ejtag_info->impcode & (1<<14))
+ return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
+ else
+ return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
default:
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
@@ -547,7 +551,11 @@
case 4:
case 2:
case 1:
- mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+ /* if noDMA off, use DMAACC mode for memory write */
+ if(ejtag_info->impcode & (1<<14))
+ mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+ else
+ mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
Index: src/target/Makefile.am
===================================================================
--- src/target/Makefile.am (revision 1022)
+++ src/target/Makefile.am (working copy)
@@ -13,11 +13,11 @@
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
- mips32_pracc.c mips_ejtag.c
+ mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
- etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h
+ etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
event/at91r40008_reset.script event/sam7x256_reset.script \
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