fabio>What has been your experience with MX27 and OpenOCD? Is it working
well?
[I added iMX27 to the subject to help others find message via search
engines]
Works for ARM mode, seems to have major problems with THUMB mode.
I'm not sure about "cache enabled" debugging. :-( - I have more testing
to do there.
Below is the OpenOCD.CFG file I am using.
PROBLEM: The board is new to me. I do not know the sdram settings yet.
(I will soon) so I let the "boot monitor" come up - initialize the
clocks & the SDRAM. If I have openOCD reset * halt - the board - then I
have to figure the SDRAM settings out :-( so instead of "reset" i
created a command "r" that does a fake (soft) reset.
meanwhile, If I use "reset halt" - I can use the 45K of "vram" without a
problem.
#====================
source [find interface/signalyzer.cfg]
jtag_khz 1000
telnet_port 4444
gdb_port 3333
gdb_memory_map enable
gdb_flash_program enable
reset_config trst_and_srst
# There are 2 taps on the chip.
# The ETM
jtag_device 4 0x1 0xf 0xe
# The ARM926EJS
jtag_device 4 0x1 0xf 0xe
# When GDB attaches, I want it to do a *SOFT* reset.
proc my_attach { } {
soft_reset_halt
}
# My "fake reset".
proc r { } {
soft_reset_halt
}
# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1)
target arm926ejs little 1 arm926ejs
# Here I tell openocd to fake a "soft reset" when I attach
[new_target_name] configure -event gdb-attach my_attach
# This is the "vram" area on the iMX27.
working_area 0 0xfff4c00 0x8000 nobackup
# This is the boot flash.
flash_bank cfi 0xc0000000 0x00200000 2 2 0
init
#===================================
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