Øyvind Harboe wrote: > I'd like to stick to C (and GCC) as the tool to describe > target algorithms. > > For MIPS/ARM this means position independent code > w/some clever entrypoint handler. > > Assuming all interesting target types can generate position > independent code: why would we want to introduce a > CPU independent language/opcodes? > See the dispatch function/interpretor/technique presented earlier.
> If you want a *small* interpreter of opcodes that can easily > be written in C/machine code, then have a look at > the ZPU. It comes complete with a toolchain. The smallest > implementation of the ZPU implements 11 *simple* instructions :-) > (http://www.zylin.com/zpu.htm). > That is an approach. Rather then very low level instructions (ie: zpu) I believe a higher level instruction might be better. For example - a single opcode that says: "download the next block of code" or maybe a single opcode that says "perform the Databit X toggle wait" this is not unlike sending high level commands to an FTDI chip and having it interpret them. -Duane. _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
