This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9565
-- gerrit commit 83a17f1884a02042e5db6e07c6bc9196ae8fd4f4 Author: Antonio Borneo <[email protected]> Date: Tue Nov 4 10:30:14 2025 +0100 tcl: stm32mp2xx: set CSW for Cortex-M33 D-Cache coherency When the D-Cache of Cortex-M33 is enabled, the memory read/write operations from debug bus and CPU should be coherent. Set Cacheable and Write-Through flags in debug bus AHB CSW to guarantee the coherency between CPU and debugger. Change-Id: I4d0541c281e8a2e2f10fe16ee313e923155a6558 Signed-off-by: Antonio Borneo <[email protected]> diff --git a/tcl/target/st/stm32mp21x.cfg b/tcl/target/st/stm32mp21x.cfg index 47d35e5afe..2cc37738bd 100644 --- a/tcl/target/st/stm32mp21x.cfg +++ b/tcl/target/st/stm32mp21x.cfg @@ -93,6 +93,10 @@ adapter srst delay 1000 $_CHIPNAME.dap apsel 2 $_CHIPNAME.dap apcsw 0x12800000 +# set CSW for Cortex-M33 D-Cache +$_CHIPNAME.dap apsel 3 +$_CHIPNAME.dap apcsw 0x1a000000 + # mmw with target selection proc target_mmw {target reg setbits clearbits} { set val [eval $target read_memory $reg 32 1] diff --git a/tcl/target/st/stm32mp23x.cfg b/tcl/target/st/stm32mp23x.cfg index 7ca1830e30..4cba8400f1 100644 --- a/tcl/target/st/stm32mp23x.cfg +++ b/tcl/target/st/stm32mp23x.cfg @@ -100,6 +100,10 @@ adapter srst delay 1000 $_CHIPNAME.dap apsel 4 $_CHIPNAME.dap apcsw 0x12800000 +# set CSW for Cortex-M33 D-Cache +$_CHIPNAME.dap apsel 8 +$_CHIPNAME.dap apcsw 0x1a000000 + # mmw with target selection proc target_mmw {target reg setbits clearbits} { set val [eval $target read_memory $reg 32 1] diff --git a/tcl/target/st/stm32mp25x.cfg b/tcl/target/st/stm32mp25x.cfg index 6ce7e0cabb..556b43ff7f 100644 --- a/tcl/target/st/stm32mp25x.cfg +++ b/tcl/target/st/stm32mp25x.cfg @@ -112,6 +112,10 @@ adapter srst delay 1000 $_CHIPNAME.dap apsel 4 $_CHIPNAME.dap apcsw 0x12800000 +# set CSW for Cortex-M33 D-Cache +$_CHIPNAME.dap apsel 8 +$_CHIPNAME.dap apcsw 0x1a000000 + # mmw with target selection proc target_mmw {target reg setbits clearbits} { set val [eval $target read_memory $reg 32 1] --
