[Icedtee Ticket #2153] -- see http://icedtea.classpath.org/bugzilla/show_bug.cgi?id=2153
This patch prevents gcc generate code on ARM5e accessing 64 bit values, because gcc doesn't ensure they're 64 bit aligned. Accessing a 64 bit value from a 32 bit alignment causes segmentation faults. Patch is taken from https://github.com/archlinuxarm/PKGBUILDs/blob/master/core/gcc/0001-ARMv5-disable-LDRD-STRD.patch Signed-off-by: Jens Rehsack <s...@netbsd.org> --- meta/recipes-devtools/gcc/gcc-4.9.inc | 1 + .../gcc/gcc-4.9/0065-ARMv5-disable-LDRD-STRD.patch | 24 ++++++++++++++++++++++ meta/recipes-devtools/gcc/gcc-5.2.inc | 1 + .../gcc/gcc-5.2/0042-ARMv5-disable-LDRD-STRD.patch | 24 ++++++++++++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 meta/recipes-devtools/gcc/gcc-4.9/0065-ARMv5-disable-LDRD-STRD.patch create mode 100644 meta/recipes-devtools/gcc/gcc-5.2/0042-ARMv5-disable-LDRD-STRD.patch diff --git a/meta/recipes-devtools/gcc/gcc-4.9.inc b/meta/recipes-devtools/gcc/gcc-4.9.inc index 691ba5f..9a1b44e 100644 --- a/meta/recipes-devtools/gcc/gcc-4.9.inc +++ b/meta/recipes-devtools/gcc/gcc-4.9.inc @@ -80,6 +80,7 @@ SRC_URI = "\ file://0062-Use-SYSTEMLIBS_DIR-replacement-instead-of-hardcoding.patch \ file://0063-nativesdk-gcc-support.patch \ file://0064-handle-target-sysroot-multilib.patch \ + file://0065-ARMv5-disable-LDRD-STRD.patch \ " SRC_URI[md5sum] = "6f831b4d251872736e8e9cc09746f327" SRC_URI[sha256sum] = "2332b2a5a321b57508b9031354a8503af6fdfb868b8c1748d33028d100a8b67e" diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0065-ARMv5-disable-LDRD-STRD.patch b/meta/recipes-devtools/gcc/gcc-4.9/0065-ARMv5-disable-LDRD-STRD.patch new file mode 100644 index 0000000..68fe3b9 --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-4.9/0065-ARMv5-disable-LDRD-STRD.patch @@ -0,0 +1,24 @@ +From b1884b6d1950422a32f9ced0be6d5492e4315547 Mon Sep 17 00:00:00 2001 +From: Kevin Mihelich <ke...@archlinuxarm.org> +Date: Wed, 7 Jan 2015 18:43:57 -0700 +Subject: [PATCH] ARMv5: disable LDRD/STRD + +--- + gcc/config/arm/arm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h +index c60d9a4..65c60b9 100644 +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -282,7 +282,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + #define TARGET_CRC32 (arm_arch_crc) +-- +2.2.1 diff --git a/meta/recipes-devtools/gcc/gcc-5.2.inc b/meta/recipes-devtools/gcc/gcc-5.2.inc index f6673e6..044e8ae 100644 --- a/meta/recipes-devtools/gcc/gcc-5.2.inc +++ b/meta/recipes-devtools/gcc/gcc-5.2.inc @@ -73,6 +73,7 @@ SRC_URI = "\ file://0039-libcc1-fix-libcc1-s-install-path-and-rpath.patch \ file://0040-nativesdk-gcc-support.patch \ file://0041-handle-target-sysroot-multilib.patch \ + file://0042-ARMv5-disable-LDRD-STRD.patch \ " BACKPORTS = "" diff --git a/meta/recipes-devtools/gcc/gcc-5.2/0042-ARMv5-disable-LDRD-STRD.patch b/meta/recipes-devtools/gcc/gcc-5.2/0042-ARMv5-disable-LDRD-STRD.patch new file mode 100644 index 0000000..68fe3b9 --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-5.2/0042-ARMv5-disable-LDRD-STRD.patch @@ -0,0 +1,24 @@ +From b1884b6d1950422a32f9ced0be6d5492e4315547 Mon Sep 17 00:00:00 2001 +From: Kevin Mihelich <ke...@archlinuxarm.org> +Date: Wed, 7 Jan 2015 18:43:57 -0700 +Subject: [PATCH] ARMv5: disable LDRD/STRD + +--- + gcc/config/arm/arm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h +index c60d9a4..65c60b9 100644 +--- a/gcc/config/arm/arm.h ++++ b/gcc/config/arm/arm.h +@@ -282,7 +282,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); + /* Thumb-1 only. */ + #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) + +-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ ++#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \ + && !TARGET_THUMB1) + + #define TARGET_CRC32 (arm_arch_crc) +-- +2.2.1 -- 2.4.3 -- Jens Rehsack - rehs...@gmail.com -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core
