SRC_URI_RISCV clears every RISC-V ISA extension via
u-boot-riscv-isa_clear.cfg, then conditionally re-adds a fragment per
TUNE_FEATURES bit: a, f, d, b/zbb, zicbom. There is no line for c, even
though u-boot-riscv-isa_c.cfg (CONFIG_RISCV_ISA_C=y) already ships in
the recipe. So for any tune with c in TUNE_FEATURES (e.g. the default
rv64gc/rv32gc tunes), compressed instructions stay disabled after the
clear fragment runs.
Building without RVC noticeably inflates .text (measured ~17.5% larger
on qemuriscv64) and, on size-constrained RISC-V SPL targets, can make
the SPL .bss VMA overlap the .text VMA and fail the link.
Add the missing "c" mapping line, mirroring the existing per-extension
entries (a, f, d, b/zbb, zicbom) already present in SRC_URI_RISCV.
Same fix as master commit fef027f2350cec0e6b890b636d2529a13f1fab58
("u-boot: re-enable RISC-V compressed (c) ISA extension"), reapplied
here since wrynose ships u-boot_2026.01.bb rather than
u-boot_2026.04.bb.
Fixes: cd9e7304481b ("u-boot: Overhaul UBOOT_CONFIG flow")
AI-Generated: Uses Cursor
Signed-off-by: Gustavo Henrique Nihei <[email protected]>
---
meta/recipes-bsp/u-boot/u-boot_2026.01.bb | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
index ac1b0b9b2b..6d9bc126a1 100644
--- a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
+++ b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
@@ -14,6 +14,7 @@ SRC_URI_RISCV = "\
${@bb.utils.contains ("TUNE_FEATURES", "a",
"file://u-boot-riscv-isa_a.cfg", "", d)} \
${@bb.utils.contains ("TUNE_FEATURES", "f",
"file://u-boot-riscv-isa_f.cfg", "", d)} \
${@bb.utils.contains ("TUNE_FEATURES", "d",
"file://u-boot-riscv-isa_d.cfg", "", d)} \
+ ${@bb.utils.contains ("TUNE_FEATURES", "c",
"file://u-boot-riscv-isa_c.cfg", "", d)} \
${@bb.utils.contains_any("TUNE_FEATURES", "b zbb",
"file://u-boot-riscv-isa_zbb.cfg", "", d)} \
${@bb.utils.contains ("TUNE_FEATURES", "zicbom",
"file://u-boot-riscv-isa_zicbom.cfg", "", d)} \
"
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