[Edited Message Follows]

I have migrated over to a Yocto build with the 6.6.52 kernel, and I am 
struggling to get the Ethernet to work. When migrating, I have noticed that the 
TX_CLK line is a constant value and not a sinusoidal clock. I have tried 
building multiple boards from the meta-3rd-party layer, however I have not been 
able to see a clock signal.

Please advise if something needs to change in my config:

pinctrl_enet2 : enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};

&fec2 {
pinctrl-names = "default" ;
pinctrl-0 = < &pinctrl_enet2 >;
phy-mode = "rmii" ;
phy-handle = < &ethphy1 >;
// phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
// phy-reset-duration = <200>;
status = "okay" ;
mdio {
#address-cells = < 1 >;
#size-cells = < 0 >;

ethphy1 : ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22" ;
clocks = < &clks IMX6UL_CLK_ENET2_REF >;
clock-names = "rmii-ref" ;
reg = < 0 >;
};
};
};

The same config worked on version 6.5.15 without these lines:

clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";

Further, when reviewing the changes, I noticed that the following changed in 
the imx6ul.dtsi file between the Yocto releases:

fec2: ethernet@20b4000 {
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x020b4000 0x4000>;
interrupt-names = "int0", "pps";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
<&clks IMX6UL_CLK_ENET2_REF_125M>,
<&clks IMX6UL_CLK_ENET2_REF_125M>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
fsl,wakeup_irq = <0>;
status = "disabled";
};

Became:

fec2: ethernet@20b4000 {
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x020b4000 0x4000>;
interrupt-names = "int0", "pps";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
<&clks IMX6UL_CLK_ENET2_REF_SEL>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
fsl,wakeup_irq = <0>;
status = "disabled";
};

Thank you for any assistance in advance.
-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#210750): 
https://lists.openembedded.org/g/openembedded-core/message/210750
Mute This Topic: https://lists.openembedded.org/mt/110987793/21656
Mute 
#bitbake:https://lists.openembedded.org/g/openembedded-core/mutehashtag/bitbake
Mute 
#scarthgap:https://lists.openembedded.org/g/openembedded-core/mutehashtag/scarthgap
Group Owner: openembedded-core+ow...@lists.openembedded.org
Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub 
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Reply via email to