On Wed, Jan 29, 2025 at 1:51 AM Randy MacLeod via lists.openembedded.org <randy.macleod=windriver....@lists.openembedded.org> wrote: > > Add Raj, Khem, Kexin and Zhe who know more about RISC-V than I do. > Kexin and Zhe are on holiday for a week or more. > CC a few people who have contributed to riscv* conf. > > I am not all that familiar with either qemu internals or riscv specifications > so any input is appreciated. > > I have some comments and questions below. > > On 2025-01-28 5:16 a.m., yash.shi...@windriver.com wrote: > > From: Yash Shinde <yash.shi...@windriver.com> > > Currently, GCC Asan supports only Sv39 on RISC-V due to custom allocator > configurations optimized for large allocations. > These configurations are incompatible with larger address spaces like > Sv48/Sv57. > This fix enables RISC-V's configuration for Sv39 by default when running > `runqemu nographic`, > eliminating the need for manual configuration via command line flags > (`qemuparams="-cpu rv64, sv39=true"`). > > Fixes [YOCTO #15691] > https://bugzilla.yoctoproject.org/show_bug.cgi?id=15691 > > Reference: > https://git.openembedded.org/openembedded-core/commit/?id=4b4450ff695ef73bf7a2437e142d2e0730d6a547 > > Signed-off-by: Yash Shinde <yash.shi...@windriver.com> > --- > meta/conf/machine/include/riscv/qemuriscv.inc | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc > b/meta/conf/machine/include/riscv/qemuriscv.inc > index d01d988eee..6170ce65f2 100644 > --- a/meta/conf/machine/include/riscv/qemuriscv.inc > +++ b/meta/conf/machine/include/riscv/qemuriscv.inc > @@ -27,6 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" > # qemuboot options > QB_SMP ?= "-smp 4" > QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" > +QB_CPU = "-cpu rv64, sv39=true" > > Thanks Yash. > > To save everyone from doing the math, sv39 gives the system 512 GB virtual > address space. > > Should we use the ?= operator here so that users can easily override this > specification > just as is done for QB_SMP two lines above? > > Please summarize what testing you did. > > Did you test with TCLIBC=musl ? > > Since you are changing qemuriscv.inc you and the YP AB should test > qemuriscv32 and qemuriscv64. > qemuriscv32 should, if I'm understanding how this works, be unaffected since > it has to use sv32 mode. > > Did you find out why sv39 isn't the default for qemu?
QEMU defaults to the max supported SATP mode. I'm not sure there is a specific reason, that's just what we have always done since we allowed a user to specify the SATP mode. > If not, please check the git history and it there isn't an answer there, ask > one of the qemu developers > who work on risc-v. It would be nice to have a sentence about that in the > commit log. > > Did you consider a different RISC-V cpu sub-arch such as rva22s64 ? I think defaulting to a profile (RVA22S64) would be the way to go, that will also enable a known set of extensions. Alistair > > > https://github.com/qemu/qemu/commit/3ba8462c4ca55720239fdc6fa30b9870d22a8814 > > I'm only asking because it seems like it might be a good fit for us and I > noticed it when > searching the qemu commit logs looking for sv39. > > > ../Randy > > > > > QB_MACHINE = "-machine virt" > QB_DEFAULT_BIOS = "fw_jump.elf" > QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" > > > -- > # Randy MacLeod > # Wind River Linux > > > >
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