On Tue, Jan 05, 2016 at 06:34:04PM +0100, Rabin Vincent wrote: > The LSR instruction cannot be used to perform a zero right shift since a > 0 as the immediate value (imm5) in the LSR instruction encoding means > that a shift of 32 is perfomed. See DecodeIMMShift() in the ARM ARM. > > Make the JIT skip generation of the LSR if a zero-shift is requested. > > This was found using american fuzzy lop. > > Signed-off-by: Rabin Vincent <ra...@rab.in>
Looks good as a fix for classic jit. For eBPF we would want to check this in verifier. Acked-by: Alexei Starovoitov <a...@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
