On Sun, Aug 23, 2015 at 11:44:01AM -0700, Florian Fainelli wrote:
> Le 08/23/15 02:46, Andrew Lunn a écrit :
> > Some Marvell switches allow the RGMII Rx and Tx clock to be delayed
> > when the port is using RGMII. Have the adjust_link function look at
> > the phy interface type and enable this delay as requested.
> >
> > Signed-off-by: Andrew Lunn <and...@lunn.ch>
> > ---
> > drivers/net/dsa/mv88e6xxx.c | 10 ++++++++++
> > drivers/net/dsa/mv88e6xxx.h | 2 ++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c
> > index 7901db6503b4..f5af368751b2 100644
> > --- a/drivers/net/dsa/mv88e6xxx.c
> > +++ b/drivers/net/dsa/mv88e6xxx.c
> > @@ -612,6 +612,16 @@ void mv88e6xxx_adjust_link(struct dsa_switch *ds, int
> > port,
> > if (phydev->duplex == DUPLEX_FULL)
> > reg |= PORT_PCS_CTRL_DUPLEX_FULL;
> >
> > + if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
> > + (port >= ps->num_ports - 2)) {
>
> Are we positive that the last two ports of a switch are going to be
> RGMII capable or is this something that should be moved to Device Tree /
> platform data to account for different switch families? Maybe having a
> bitmask of RGMII capable ports stored in "ps" would be good enough?
Hi Florian
For these two families, this is correct. And it is a property of the
switch, not the board, so should not be in DT. Other families are
different. Older ones are Fast Ethernet only. Some don't have any
RGMII ports, etc. It could be with time, this condition gets messy, at
which point, a bitmask in ps would make sense. But is it justified
now?
Thanks
Andrew
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