On 9/12/07, Stephen Hemminger <[EMAIL PROTECTED]> wrote: > But if you compare this to non-NAPI driver the same softirq > overhead happens. The problem is that for many older devices disabling IRQ's > require an expensive non-cached PCI access. Smarter, newer devices > all use MSI which is pure edge triggered and with proper register > usage, NAPI should be no worse than non-NAPI.
Why would disabling IRQ's be expensive on non-MSI PCI devices? Wouldn't it just require a single MMIO write to clear the interrupt mask of the device. These are write-buffered so the latency should be minimal. As mentioned in Jamal's UKUUG paper, any MMIO reading could be avoided by caching the interrupt mask. - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
