Christoph Hellwig wrote:
On Thu, May 17, 2007 at 09:58:03AM -0500, Wen Xiong wrote:
It really shouldn't be there at all because something in either the
intel
or pseries hardware is totally buggy and we should disable features in
the buggy one completely.
Hi,
Here there are not hardware issue on both Intel or PPC. The patch is to
work around a loop hold on early version of PCI SGI spec.
The later PCI Sgi have spec have corrected it. We can just implement it
for PPC only. Other vendor may have the same issue.
In this case we should add a blacklist for implementations of the old
spec. There should be a way to find specific bridges in the OF firmware
tree on powerpc and similar things on other platforms aswell.
Yes, this is almost what we did.
IBM is currently testing my patches that implement a generic pci quirk that will
be enabled for only selected root complex ID's that require the (1.0a spec)
device to disable the completion timeouts.
They are currently validating this test on the affected hardware. I expect to
get the results within a week and then I will post the patch.
Since this is one of the few holes in between the two specs (where manual
intervention is needed) I think that a single quirk is a fairly sane approach.
Cheers,
Auke
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