On 4/4/21 10:23 PM, Leon Romanovsky wrote:
> diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
> index bed4cfe50554..59138174affa 100644
> --- a/include/rdma/ib_verbs.h
> +++ b/include/rdma/ib_verbs.h
> @@ -2444,10 +2444,10 @@ struct ib_device_ops {
> struct ib_udata *udata);
> int (*dereg_mr)(struct ib_mr *mr, struct ib_udata *udata);
> struct ib_mr *(*alloc_mr)(struct ib_pd *pd, enum ib_mr_type mr_type,
> - u32 max_num_sg);
> + u32 max_num_sg, u32 access);
> struct ib_mr *(*alloc_mr_integrity)(struct ib_pd *pd,
> u32 max_num_data_sg,
> - u32 max_num_meta_sg);
> + u32 max_num_meta_sg, u32 access);
> int (*advise_mr)(struct ib_pd *pd,
> enum ib_uverbs_advise_mr_advice advice, u32 flags,
> struct ib_sge *sg_list, u32 num_sge,
> @@ -4142,11 +4142,10 @@ static inline int ib_dereg_mr(struct ib_mr *mr)
> }
>
> struct ib_mr *ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
> - u32 max_num_sg);
> + u32 max_num_sg, u32 access);
>
> -struct ib_mr *ib_alloc_mr_integrity(struct ib_pd *pd,
> - u32 max_num_data_sg,
> - u32 max_num_meta_sg);
> +struct ib_mr *ib_alloc_mr_integrity(struct ib_pd *pd, u32 max_num_data_sg,
> + u32 max_num_meta_sg, u32 access);
>
> /**
> * ib_update_fast_reg_key - updates the key portion of the fast_reg MR
> diff --git a/include/rdma/mr_pool.h b/include/rdma/mr_pool.h
> index e77123bcb43b..2a0ee791037d 100644
> --- a/include/rdma/mr_pool.h
> +++ b/include/rdma/mr_pool.h
> @@ -11,7 +11,8 @@ struct ib_mr *ib_mr_pool_get(struct ib_qp *qp, struct
> list_head *list);
> void ib_mr_pool_put(struct ib_qp *qp, struct list_head *list, struct ib_mr
> *mr);
>
> int ib_mr_pool_init(struct ib_qp *qp, struct list_head *list, int nr,
> - enum ib_mr_type type, u32 max_num_sg, u32 max_num_meta_sg);
> + enum ib_mr_type type, u32 max_num_sg, u32 max_num_meta_sg,
> + u32 access);
> void ib_mr_pool_destroy(struct ib_qp *qp, struct list_head *list);
>
> #endif /* _RDMA_MR_POOL_H */
Does the new 'access' argument only control whether or not PCIe relaxed
ordering is enabled? It seems wrong to me to make enabling of PCIe
relaxed ordering configurable. I think this mechanism should be enabled
unconditionally if the HCA supports it.
Thanks,
Bart.
